Simulation Results: keymgr

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.93 %
  • code
  • 95.42 %
  • assert
  • 97.72 %
  • func
  • 67.66 %
  • line
  • 98.88 %
  • branch
  • 96.62 %
  • cond
  • 93.24 %
  • toggle
  • 97.66 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.050s 510.623us 1 1 100.00
random 1 1 100.00
keymgr_random 3.020s 347.506us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.120s 79.230us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 8.010s 1519.727us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.200s 238.561us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.160s 23.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
keymgr_csr_aliasing 5.200s 238.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 24.610s 674.714us 1 1 100.00
sideload 3 4 75.00
keymgr_sideload 0.760s 2.921us 0 1 0.00
keymgr_sideload_kmac 2.240s 222.842us 1 1 100.00
keymgr_sideload_aes 1.760s 36.190us 1 1 100.00
keymgr_sideload_otbn 9.120s 498.573us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.760s 62.894us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.200s 165.065us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.900s 288.379us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.500s 79.302us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.620s 111.269us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 9.890s 682.983us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 33.930s 1411.634us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.700s 27.728us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.770s 13.508us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.840s 397.623us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.840s 397.623us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.120s 79.230us 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
keymgr_csr_aliasing 5.200s 238.561us 1 1 100.00
keymgr_same_csr_outstanding 2.020s 139.170us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.120s 79.230us 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
keymgr_csr_aliasing 5.200s 238.561us 1 1 100.00
keymgr_same_csr_outstanding 2.020s 139.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
keymgr_tl_intg_err 3.180s 1231.684us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.010s 223.665us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.010s 223.665us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.010s 223.665us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.010s 223.665us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.910s 557.376us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.180s 1231.684us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.010s 223.665us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 24.610s 674.714us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.020s 347.506us 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.020s 347.506us 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.020s 347.506us 1 1 100.00
keymgr_csr_rw 0.910s 175.358us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.200s 165.065us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.620s 111.269us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.620s 111.269us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.020s 347.506us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.360s 47.243us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.180s 271.187us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.200s 165.065us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.180s 271.187us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.180s 271.187us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.180s 271.187us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.190s 1130.880us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.180s 271.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 7.340s 269.245us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_sideload 40169058215209539373111111684330723327505559592322145635068251328527374248742 99
UVM_INFO @ 2920730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---