Simulation Results: kmac/masked

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.51 %
  • code
  • 89.85 %
  • assert
  • 98.70 %
  • func
  • 94.99 %
  • line
  • 98.74 %
  • branch
  • 96.00 %
  • cond
  • 91.02 %
  • toggle
  • 99.43 %
  • FSM
  • 64.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 69.150s 4405.111us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 58.239us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.390s 17.058us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.970s 2966.298us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.220s 138.784us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.390s 185.231us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.390s 17.058us 1 1 100.00
kmac_csr_aliasing 5.220s 138.784us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 22.879us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.150s 22.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2792.080s 29895.372us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 414.930s 16366.854us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1568.520s 19439.702us 1 1 100.00
kmac_test_vectors_sha3_256 2301.270s 912473.500us 1 1 100.00
kmac_test_vectors_sha3_384 1415.610s 68798.467us 1 1 100.00
kmac_test_vectors_sha3_512 847.760s 37944.584us 1 1 100.00
kmac_test_vectors_shake_128 2931.100s 120931.417us 1 1 100.00
kmac_test_vectors_shake_256 354.440s 33042.799us 1 1 100.00
kmac_test_vectors_kmac 2.740s 213.873us 1 1 100.00
kmac_test_vectors_kmac_xof 2.170s 89.351us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 169.940s 108533.180us 1 1 100.00
app 1 1 100.00
kmac_app 35.780s 2103.578us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 179.360s 27907.062us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 330.580s 22055.730us 1 1 100.00
error 1 1 100.00
kmac_error 143.660s 7602.769us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 9.390s 1727.775us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.130s 34.424us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 15.200s 5301.449us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.890s 59.459us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 48.670s 20520.827us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.220s 108.513us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 141.710s 26191.767us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.140s 56.205us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.770s 218.482us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.460s 619.252us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.460s 619.252us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 58.239us 1 1 100.00
kmac_csr_rw 1.390s 17.058us 1 1 100.00
kmac_csr_aliasing 5.220s 138.784us 1 1 100.00
kmac_same_csr_outstanding 1.880s 66.453us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 58.239us 1 1 100.00
kmac_csr_rw 1.390s 17.058us 1 1 100.00
kmac_csr_aliasing 5.220s 138.784us 1 1 100.00
kmac_same_csr_outstanding 1.880s 66.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.630s 287.733us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.630s 287.733us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.630s 287.733us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.630s 287.733us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.170s 234.239us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 38.810s 6971.774us 1 1 100.00
kmac_tl_intg_err 2.370s 56.808us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.370s 56.808us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.220s 108.513us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 69.150s 4405.111us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 169.940s 108533.180us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.630s 287.733us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 38.810s 6971.774us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 38.810s 6971.774us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 38.810s 6971.774us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 69.150s 4405.111us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.220s 108.513us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 38.810s 6971.774us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 292.590s 30694.085us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 69.150s 4405.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 54.210s 2515.190us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 78952281068039090225509871322669079359660408732190099336885689998839700715651 212
UVM_INFO @ 2515190351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---