Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.88 %
  • code
  • 83.90 %
  • assert
  • 94.97 %
  • func
  • 93.77 %
  • line
  • 97.24 %
  • branch
  • 93.85 %
  • cond
  • 79.15 %
  • toggle
  • 85.70 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.930s 67.082us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.290s 46.265us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 45.389us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.230s 244.939us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 248.225us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 52.049us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 45.389us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 248.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.440s 137.770us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 657.453us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.830s 38.744us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.650s 110.352us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.460s 404.030us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_prog_failure 2.650s 110.352us 1 1 100.00
lc_ctrl_errors 5.460s 404.030us 1 1 100.00
lc_ctrl_security_escalation 4.000s 251.584us 1 1 100.00
lc_ctrl_jtag_state_failure 18.180s 4837.724us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.410s 439.771us 1 1 100.00
lc_ctrl_jtag_errors 27.820s 12223.611us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.440s 522.024us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.790s 2721.239us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.410s 439.771us 1 1 100.00
lc_ctrl_jtag_errors 27.820s 12223.611us 1 1 100.00
lc_ctrl_jtag_access 11.360s 3038.040us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.220s 2803.635us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.360s 49.351us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.700s 89.014us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.590s 13272.537us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.640s 1054.112us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.600s 49.843us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.560s 1317.310us 1 1 100.00
lc_ctrl_jtag_alert_test 1.690s 198.796us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.440s 464.539us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 64.888us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.470s 2530.249us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.420s 74.960us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.980s 65.843us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.980s 65.843us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.290s 46.265us 1 1 100.00
lc_ctrl_csr_rw 0.910s 45.389us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 248.225us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 47.023us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.290s 46.265us 1 1 100.00
lc_ctrl_csr_rw 0.910s 45.389us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 248.225us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 47.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
lc_ctrl_tl_intg_err 1.150s 52.590us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.150s 52.590us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 657.453us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.820s 146.568us 1 1 100.00
lc_ctrl_sec_cm 5.670s 135.981us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 251.584us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.440s 137.770us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.790s 2721.239us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.660s 233.537us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.660s 233.537us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.930s 1560.944us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.040s 3584.847us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.040s 3584.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.930s 11041.586us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 47054659854735521740640886534476135725558120346110625225588042821414508585357 2252
UVM_INFO @ 11041585684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---