Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.92 %
  • code
  • 83.99 %
  • assert
  • 94.83 %
  • func
  • 93.95 %
  • line
  • 97.08 %
  • branch
  • 93.37 %
  • cond
  • 79.34 %
  • toggle
  • 86.61 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.160s 64.124us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 54.879us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 25.168us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.750s 1248.038us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 97.061us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 67.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 25.168us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 97.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.440s 460.463us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.600s 283.593us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 14.799us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.250s 105.836us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.920s 671.796us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_prog_failure 2.250s 105.836us 1 1 100.00
lc_ctrl_errors 6.920s 671.796us 1 1 100.00
lc_ctrl_security_escalation 7.590s 365.256us 1 1 100.00
lc_ctrl_jtag_state_failure 29.910s 5584.205us 1 1 100.00
lc_ctrl_jtag_prog_failure 19.470s 4208.874us 1 1 100.00
lc_ctrl_jtag_errors 15.160s 1392.419us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.820s 48.740us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.810s 1971.419us 1 1 100.00
lc_ctrl_jtag_prog_failure 19.470s 4208.874us 1 1 100.00
lc_ctrl_jtag_errors 15.160s 1392.419us 1 1 100.00
lc_ctrl_jtag_access 6.000s 1127.853us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.250s 1185.465us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.430s 85.708us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.330s 46.146us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.210s 673.930us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.740s 5650.587us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.610s 90.892us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.840s 371.016us 1 1 100.00
lc_ctrl_jtag_alert_test 1.030s 49.602us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.810s 493.764us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 17.390us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 9.640s 564.985us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 30.060us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 28.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 28.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 54.879us 1 1 100.00
lc_ctrl_csr_rw 0.930s 25.168us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 97.061us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 41.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 54.879us 1 1 100.00
lc_ctrl_csr_rw 0.930s 25.168us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 97.061us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 41.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
lc_ctrl_tl_intg_err 1.270s 971.420us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.270s 971.420us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.600s 283.593us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.390s 1184.333us 1 1 100.00
lc_ctrl_sec_cm 6.530s 224.214us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.590s 365.256us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.440s 460.463us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.810s 1971.419us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.220s 1632.281us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.220s 1632.281us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.140s 437.375us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.780s 1740.607us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.780s 1740.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 28.330s 11550.849us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 18899798602905633142296985590780057467724683433288690341252231607718520983815 1797
UVM_INFO @ 564985365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 66642039476827226101272585189672749409817814413787269257901714372169708267894 4112
UVM_INFO @ 11550848838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---