Simulation Results: otbn

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.45 %
  • code
  • 94.28 %
  • assert
  • 90.33 %
  • func
  • 98.73 %
  • block
  • 99.34 %
  • line
  • 99.51 %
  • branch
  • 91.62 %
  • toggle
  • 88.42 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 17.000s 295.100us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 21.000s 24.044us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 20.000s 25.064us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 22.000s 75.849us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 21.000s 63.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 21.000s 42.108us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 20.000s 25.064us 1 1 100.00
otbn_csr_aliasing 21.000s 63.728us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 45.000s 2086.089us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 33.000s 1428.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 335.902us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 54.000s 332.110us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 21.000s 57.165us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 77.000s 241.161us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 13.000s 112.234us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 28.845us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 13.000s 51.396us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 24.000s 29.362us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 36.672us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 108.845us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 108.845us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 21.000s 24.044us 1 1 100.00
otbn_csr_rw 20.000s 25.064us 1 1 100.00
otbn_csr_aliasing 21.000s 63.728us 1 1 100.00
otbn_same_csr_outstanding 3.000s 85.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 21.000s 24.044us 1 1 100.00
otbn_csr_rw 20.000s 25.064us 1 1 100.00
otbn_csr_aliasing 21.000s 63.728us 1 1 100.00
otbn_same_csr_outstanding 3.000s 85.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 13.912us 1 1 100.00
otbn_dmem_err 24.000s 62.995us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 28.000s 61.713us 1 1 100.00
otbn_controller_ispr_rdata_err 23.000s 425.833us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 199.815us 1 1 100.00
otbn_urnd_err 10.000s 40.167us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 103.456us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 78.911us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 20.895us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
otbn_tl_intg_err 19.000s 188.102us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 40.000s 182.498us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 295.100us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 24.000s 62.995us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 13.912us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 19.000s 188.102us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 112.234us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 13.912us 1 1 100.00
otbn_dmem_err 24.000s 62.995us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 28.845us 1 1 100.00
otbn_illegal_mem_acc 9.000s 103.456us 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 13.912us 1 1 100.00
otbn_dmem_err 24.000s 62.995us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 28.845us 1 1 100.00
otbn_illegal_mem_acc 9.000s 103.456us 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 112.234us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 13.912us 1 1 100.00
otbn_dmem_err 24.000s 62.995us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 28.845us 1 1 100.00
otbn_illegal_mem_acc 9.000s 103.456us 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 26.000s 41.848us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 38.036us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 119.687us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 119.687us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 26.362us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 72.969us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 13.613us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 13.613us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 58.134us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 21.000s 57.165us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 61.918us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 175.850us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 443.000s 2909.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 222.000s 1450.304us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 116.570us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 50600202382808292174754844100924205817481272877946218774564275058677198290489 157
UVM_INFO @ 57164957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 14191235821627387386161620437308001127140732672327612376801578191634642942877 382
UVM_INFO @ 1450303806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---