Simulation Results: otp_ctrl

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.16 %
  • code
  • 79.98 %
  • assert
  • 93.99 %
  • func
  • 78.50 %
  • line
  • 88.57 %
  • branch
  • 83.50 %
  • cond
  • 90.49 %
  • toggle
  • 88.57 %
  • FSM
  • 48.78 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.810s 58.132us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.510s 105.757us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.430s 49.398us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.940s 84.312us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.350s 1688.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.390s 146.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.430s 49.398us 1 1 100.00
otp_ctrl_csr_aliasing 3.350s 1688.593us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.390s 40.022us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.330s 116.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.780s 1253.093us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.400s 113.581us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 33.740s 4506.763us 1 1 100.00
otp_ctrl_check_fail 11.100s 646.338us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.650s 623.314us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 14.500s 8574.670us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.070s 1545.198us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.670s 3383.409us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.850s 112.642us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 13.570s 917.923us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 222.430s 25043.392us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.240s 147.682us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.210s 55.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.450s 2336.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.450s 2336.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.510s 105.757us 1 1 100.00
otp_ctrl_csr_rw 1.430s 49.398us 1 1 100.00
otp_ctrl_csr_aliasing 3.350s 1688.593us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.870s 138.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.510s 105.757us 1 1 100.00
otp_ctrl_csr_rw 1.430s 49.398us 1 1 100.00
otp_ctrl_csr_aliasing 3.350s 1688.593us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.870s 138.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
otp_ctrl_tl_intg_err 15.870s 9851.532us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.870s 9851.532us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_macro_errs 1.850s 112.642us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_macro_errs 1.850s 112.642us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.590s 339.334us 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.400s 113.581us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 11.100s 646.338us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.450s 2638.325us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.900s 43481.662us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.650s 623.314us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.580s 94.447us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.850s 112.642us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.150s 3047.418us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 74.880s 13315.494us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 34588114660100102901763760318805756159095043596071177786150504209046842627069 111
UVM_INFO @ 112641732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 3760420974710314756842127783143283558125668886794769778589898194183979371909 20423
UVM_INFO @ 13315494372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---