| V1 |
|
100.00% |
| V2 |
|
90.91% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwm_smoke | 4.000s | 523.816us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 15.010us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwm_csr_rw | 1.000s | 35.321us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwm_csr_bit_bash | 5.000s | 2967.999us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwm_csr_aliasing | 2.000s | 240.895us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwm_csr_mem_rw_with_rand_reset | 2.000s | 33.740us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwm_csr_rw | 1.000s | 35.321us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 240.895us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dutycycle | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| pulse | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| blink | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| heartbeat | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| resolution | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| multi_channel | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| polarity | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| phase | 2 | 2 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| pwm_phase | 31.000s | 11020.126us | 1 | 1 | 100.00 | |
| lowpower | 1 | 1 | 100.00 | |||
| pwm_rand_output | 43.000s | 10610.492us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| pwm_perf | 26.000s | 40388.640us | 1 | 1 | 100.00 | |
| regwen | 0 | 1 | 0.00 | |||
| pwm_regwen | 302.000s | 41966.335us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| pwm_stress_all | 144.000s | 81833.043us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| pwm_alert_test | 2.000s | 26.006us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 2.000s | 438.001us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 2.000s | 438.001us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 15.010us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 1.000s | 35.321us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 240.895us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 2.000s | 36.516us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 15.010us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 1.000s | 35.321us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 240.895us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 2.000s | 36.516us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| pwm_tl_intg_err | 2.000s | 965.918us | 1 | 1 | 100.00 | |
| pwm_sec_cm | 2.000s | 403.633us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| pwm_tl_intg_err | 2.000s | 965.918us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| heartbeat_wrap | 1 | 1 | 100.00 | |||
| pwm_heartbeat_wrap | 24.000s | 10509.730us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (pwm_scoreboard.sv:386) scoreboard [scoreboard] | 1 test run | |||
| pwm_regwen | 47106559710501440654494681753061225656105097192338814031704191095468772421280 | 101 |
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 41966334941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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