Simulation Results: pwrmgr

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.40 %
  • code
  • 92.91 %
  • assert
  • 98.43 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.47 %
  • toggle
  • 99.62 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.660s 37.440us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 25.412us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.620s 375.912us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.910s 170.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.810s 44.844us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 170.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.220s 267.909us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.220s 267.909us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.640s 59.056us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 52.467us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.940s 88.059us 1 1 100.00
pwrmgr_reset_invalid 0.660s 67.152us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.940s 88.059us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.960s 145.852us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.840s 329.641us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.700s 97.053us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.750s 94.832us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 26.034us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.860s 46.974us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.860s 46.974us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 25.412us 1 1 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 170.903us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 22.186us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 25.412us 1 1 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 170.903us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 22.186us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.970s 264.773us 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.970s 264.773us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.590s 860.551us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.960s 145.852us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.860s 946.251us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.880s 68.844us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.640s 28.967us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.330s 804.232us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 44.367us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 42.343us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.620s 42.868us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 28.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.750s 359.311us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.020s 4283.778us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks 1 test run
pwrmgr_reset_invalid 37549578882945818510022862790409761659384131214228269473450972369470791009132 123
UVM_INFO @ 67151737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---