Simulation Results: rom_ctrl/32kb

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.59 %
  • code
  • 98.06 %
  • assert
  • 97.09 %
  • func
  • 97.61 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 99.54 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.180s 671.725us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.900s 565.025us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.230s 178.363us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.440s 170.533us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.680s 534.821us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.200s 314.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.230s 178.363us 1 1 100.00
rom_ctrl_csr_aliasing 3.680s 534.821us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.430s 277.804us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.780s 533.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.430s 639.711us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.380s 1640.199us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.380s 2819.881us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.570s 123.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.590s 191.796us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.590s 191.796us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.900s 565.025us 1 1 100.00
rom_ctrl_csr_rw 4.230s 178.363us 1 1 100.00
rom_ctrl_csr_aliasing 3.680s 534.821us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.260s 209.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.900s 565.025us 1 1 100.00
rom_ctrl_csr_rw 4.230s 178.363us 1 1 100.00
rom_ctrl_csr_aliasing 3.680s 534.821us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.260s 209.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.710s 588.210us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
rom_ctrl_tl_intg_err 45.780s 419.497us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.180s 671.725us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.180s 671.725us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.180s 671.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 45.780s 419.497us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
rom_ctrl_kmac_err_chk 7.380s 2819.881us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 44.300s 1234.743us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.710s 588.210us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 232.210s 2195.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 404.940s 19680.093us 1 1 100.00