Simulation Results: rom_ctrl/64kb

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 97.78 %
  • assert
  • 97.24 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 98.91 %
  • cond
  • 97.47 %
  • toggle
  • 99.62 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.620s 307.082us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.550s 299.784us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.100s 4136.740us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.790s 384.062us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 288.087us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.770s 469.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.100s 4136.740us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 288.087us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.060s 4119.667us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.580s 1137.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 9.110s 566.005us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.910s 1722.986us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.980s 545.756us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.810s 369.914us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.810s 287.115us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.810s 287.115us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.550s 299.784us 1 1 100.00
rom_ctrl_csr_rw 9.100s 4136.740us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 288.087us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.090s 212.625us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.550s 299.784us 1 1 100.00
rom_ctrl_csr_rw 9.100s 4136.740us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 288.087us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.090s 212.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.740s 2134.175us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
rom_ctrl_tl_intg_err 100.140s 1525.780us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.620s 307.082us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.620s 307.082us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.620s 307.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.140s 1525.780us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
rom_ctrl_kmac_err_chk 14.980s 545.756us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.240s 45967.541us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.740s 2134.175us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 239.180s 482.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 154.230s 9742.764us 1 1 100.00