Simulation Results: rstmgr

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.47 %
  • code
  • 99.22 %
  • assert
  • 98.93 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.090s 117.611us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.150s 147.410us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.470s 274.039us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.010s 230.943us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.040s 149.110us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00
rstmgr_csr_aliasing 2.010s 230.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.780s 136.317us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.350s 388.655us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.950s 118.998us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.260s 944.949us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.260s 944.949us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.260s 944.949us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.260s 944.949us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.170s 3160.467us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.080s 69.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.700s 341.538us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.700s 341.538us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 147.410us 1 1 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00
rstmgr_csr_aliasing 2.010s 230.943us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 138.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 147.410us 1 1 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00
rstmgr_csr_aliasing 2.010s 230.943us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 138.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.320s 17054.744us 1 1 100.00
rstmgr_tl_intg_err 1.680s 513.241us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.320s 17054.744us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.320s 17054.744us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.680s 513.241us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.470s 189.691us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.730s 2437.170us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.230s 301.410us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.320s 17054.744us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 61.441us 1 1 100.00