Simulation Results: rv_timer

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.60 %
  • code
  • 100.00 %
  • assert
  • 98.09 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.800s 329.445us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 18.150us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 22.555us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.230s 283.280us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.740s 24.862us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 26.746us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 22.555us 1 1 100.00
rv_timer_csr_aliasing 0.740s 24.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.690s 66.593us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.080s 1862.905us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 392.050s 1412646.342us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 392.050s 1412646.342us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.140s 4727.815us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.660s 14.645us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 47.775us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.110s 418.036us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.110s 418.036us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 18.150us 1 1 100.00
rv_timer_csr_rw 0.630s 22.555us 1 1 100.00
rv_timer_csr_aliasing 0.740s 24.862us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 48.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 18.150us 1 1 100.00
rv_timer_csr_rw 0.630s 22.555us 1 1 100.00
rv_timer_csr_aliasing 0.740s 24.862us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 48.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 94.826us 1 1 100.00
rv_timer_tl_intg_err 0.990s 85.609us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.990s 85.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.740s 80.997us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.640s 45.194us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 22.160s 2883.733us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 100358620536648497706835820148762708193542455514142709857418189735237836203583 75
UVM_INFO @ 80996581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 114170157375487086526257625464027018662710360181377989722179786531706653376575 75
UVM_INFO @ 66592649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 53631716665062546132781251951374273659397125241022791246069996037468340856858 75
UVM_INFO @ 45194202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---