Simulation Results: spi_device/2p

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 93.99 %
  • assert
  • 95.37 %
  • func
  • 72.67 %
  • line
  • 98.90 %
  • branch
  • 98.30 %
  • cond
  • 95.64 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 26.110s 7873.391us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.320s 60.709us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.630s 494.241us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.060s 1455.877us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.670s 412.535us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.860s 29.474us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.630s 494.241us 1 1 100.00
spi_device_csr_aliasing 6.670s 412.535us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 17.764us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.120s 18.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.870s 68.695us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.930s 53.909us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.810s 38.427us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.010s 139.396us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.010s 139.396us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.060s 941.902us 1 1 100.00
spi_device_tpm_sts_read 0.770s 35.264us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.850s 4688.375us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.130s 265.193us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.570s 2888.992us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.570s 2888.992us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.530s 5668.382us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.530s 5668.382us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.530s 5668.382us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.530s 5668.382us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.530s 5668.382us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.960s 863.861us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.150s 23403.743us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.150s 23403.743us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.150s 23403.743us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.230s 633.728us 1 1 100.00
spi_device_read_buffer_direct 4.420s 839.128us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.150s 23403.743us 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 177.760s 43067.618us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.230s 11007.708us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.230s 11007.708us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 58.510s 17222.096us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 26.110s 7873.391us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 55.520s 29308.621us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 583.080s 251746.315us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.700s 113.540us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.820s 12.171us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.780s 142.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.780s 142.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.320s 60.709us 1 1 100.00
spi_device_csr_rw 1.630s 494.241us 1 1 100.00
spi_device_csr_aliasing 6.670s 412.535us 1 1 100.00
spi_device_same_csr_outstanding 3.380s 816.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.320s 60.709us 1 1 100.00
spi_device_csr_rw 1.630s 494.241us 1 1 100.00
spi_device_csr_aliasing 6.670s 412.535us 1 1 100.00
spi_device_same_csr_outstanding 3.380s 816.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.200s 90.723us 1 1 100.00
spi_device_tl_intg_err 6.380s 1297.592us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.380s 1297.592us 1 1 100.00