Simulation Results: sram_ctrl/main

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 96.80 %
  • assert
  • 97.96 %
  • func
  • 95.60 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 95.99 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 4178.518us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 67.229us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 51.523us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 442.570us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.516us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1426.261us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 51.523us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.516us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 80.000s 2060.405us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 47.000s 2553.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 31.000s 67848.488us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 179.000s 8180.421us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 144.000s 27145.189us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 24.000s 11479.524us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11358.899us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 31.000s 6375.112us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 711.820us 1 1 100.00
sram_ctrl_partial_access_b2b 174.000s 56161.671us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 671.201us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 701.811us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 693.465us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 6233.961us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.000s 2811.770us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 64.000s 50986.713us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 40.606us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 49.411us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 49.411us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 67.229us 1 1 100.00
sram_ctrl_csr_rw 1.000s 51.523us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.516us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.191us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 67.229us 1 1 100.00
sram_ctrl_csr_rw 1.000s 51.523us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.516us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 41.000s 100738.636us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 298.962us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 298.962us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 6233.961us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 6233.961us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 51.523us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 31.000s 6375.112us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 6375.112us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 6375.112us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11358.899us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1381.823us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 41.000s 100738.636us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 696.635us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 4178.518us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 4178.518us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 31.000s 6375.112us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11358.899us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 4178.518us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 331.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 4881.060us 1 1 100.00