Simulation Results: uart

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.03 %
  • code
  • 96.24 %
  • assert
  • 98.85 %
  • func
  • 54.01 %
  • line
  • 99.48 %
  • branch
  • 97.90 %
  • cond
  • 96.03 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.610s 673.789us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 14.348us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.720s 44.045us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.870s 60.266us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.850s 28.774us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.960s 27.952us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.720s 44.045us 1 1 100.00
uart_csr_aliasing 0.850s 28.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 57.830s 56288.703us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.610s 673.789us 1 1 100.00
uart_tx_rx 57.830s 56288.703us 1 1 100.00
parity_error 2 2 100.00
uart_intr 7.310s 20557.712us 1 1 100.00
uart_rx_parity_err 101.660s 86629.860us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 57.830s 56288.703us 1 1 100.00
uart_intr 7.310s 20557.712us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 69.460s 143932.157us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 43.760s 147866.030us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 99.890s 106440.391us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 7.310s 20557.712us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 7.310s 20557.712us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 7.310s 20557.712us 1 1 100.00
perf 1 1 100.00
uart_perf 64.570s 6407.941us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.810s 6508.571us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.810s 6508.571us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.440s 2310.702us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.250s 854.723us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.450s 929.166us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.240s 6384.406us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 381.550s 118687.916us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 557.870s 185210.974us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 21.196us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.630s 14.956us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.240s 66.664us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.240s 66.664us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 14.348us 1 1 100.00
uart_csr_rw 0.720s 44.045us 1 1 100.00
uart_csr_aliasing 0.850s 28.774us 1 1 100.00
uart_same_csr_outstanding 1.020s 20.521us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 14.348us 1 1 100.00
uart_csr_rw 0.720s 44.045us 1 1 100.00
uart_csr_aliasing 0.850s 28.774us 1 1 100.00
uart_same_csr_outstanding 1.020s 20.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.200s 66.211us 1 1 100.00
uart_tl_intg_err 1.190s 502.410us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.190s 502.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 12.440s 630.484us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 32831466020959168159955132832674220698129115364811199322729720344469980220666 76
UVM_ERROR @ 1050150844 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1050161261 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (39 [0x27] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1130820092 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1130820092 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1