Simulation Results: adc_ctrl

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.61 %
  • code
  • 93.22 %
  • assert
  • 92.06 %
  • func
  • 11.54 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.98 %
  • toggle
  • 99.29 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.960s 5774.621us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.450s 1163.402us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.350s 458.636us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 39.750s 52643.133us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.300s 678.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.050s 647.982us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.350s 458.636us 1 1 100.00
adc_ctrl_csr_aliasing 1.300s 678.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.240s 449.599us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.140s 385.801us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.730s 400.152us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.770s 269.033us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.690s 346.486us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.760s 500.408us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.800s 459.066us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.830s 338.010us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.190s 4518.350us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.210s 29529.234us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 169.060s 93860.203us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 3.670s 7939.971us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.950s 378.260us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.330s 481.622us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.170s 495.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.170s 495.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.450s 1163.402us 1 1 100.00
adc_ctrl_csr_rw 1.350s 458.636us 1 1 100.00
adc_ctrl_csr_aliasing 1.300s 678.452us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.740s 4718.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.450s 1163.402us 1 1 100.00
adc_ctrl_csr_rw 1.350s 458.636us 1 1 100.00
adc_ctrl_csr_aliasing 1.300s 678.452us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.740s 4718.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.050s 4992.561us 1 1 100.00
adc_ctrl_tl_intg_err 5.090s 8560.578us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 5.090s 8560.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.510s 1940.280us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 61295009118246119079207797253926676237875211621087755930967392282692221754 386
UVM_INFO @ 449598859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 93378163761777810105971081009987762550369108232139159072692995606366063433397 386
UVM_INFO @ 385801121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 11640256798852811092652275178049145966478935716071102109847380015830144456993 386
UVM_INFO @ 400152423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 11700816434519384428379811569486428692727703088190638416903324119622052770344 386
UVM_INFO @ 269033383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 7803925028319590213306299929627150626772669995164731164458196023591249643003 386
UVM_INFO @ 346486396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 57228414208524252801093810714604653305768751425847508809884389052673983055867 386
UVM_INFO @ 500408441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 14752064099046555854831041204721320695122848713309059536433994625084701603318 386
UVM_INFO @ 338009615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 87742202514727949999962598678183957958349069397061742534414687394514546483368 386
UVM_INFO @ 459066448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 7731274614265262761297862743664739114308330111235320040868694293269899072142 410
UVM_INFO @ 1940279659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 42770267870650556418904822817146986979659602882324581864251770696205164501268 411
UVM_INFO @ 7939970760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---