Simulation Results: aes/masked

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 93.12 %
  • assert
  • 98.23 %
  • func
  • 71.51 %
  • block
  • 94.16 %
  • line
  • 95.75 %
  • branch
  • 86.88 %
  • toggle
  • 97.99 %
  • FSM
  • 91.85 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 106.200us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 318.251us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 53.414us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 62.085us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 4494.496us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 1205.846us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 63.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 62.085us 1 1 100.00
aes_csr_aliasing 3.000s 1205.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 318.251us 1 1 100.00
aes_config_error 3.000s 164.449us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 318.251us 1 1 100.00
aes_config_error 3.000s 164.449us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_b2b 4.000s 309.996us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 318.251us 1 1 100.00
aes_config_error 3.000s 164.449us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 93.895us 1 1 100.00
aes_config_error 3.000s 164.449us 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 104.636us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 883.627us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_sideload 3.000s 104.901us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 68.393us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 17.000s 1814.339us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 58.352us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 102.242us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 102.242us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 53.414us 1 1 100.00
aes_csr_rw 1.000s 62.085us 1 1 100.00
aes_csr_aliasing 3.000s 1205.846us 1 1 100.00
aes_same_csr_outstanding 2.000s 193.124us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 53.414us 1 1 100.00
aes_csr_rw 1.000s 62.085us 1 1 100.00
aes_csr_aliasing 3.000s 1205.846us 1 1 100.00
aes_same_csr_outstanding 2.000s 193.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 228.818us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 237.334us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 13.000s 3530.646us 1 1 100.00
aes_tl_intg_err 3.000s 353.014us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 353.014us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 318.251us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
aes_core_fi 3.000s 92.697us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 164.449us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_core_fi 3.000s 92.697us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.609us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 60.672us 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 453.393us 1 1 100.00
aes_sideload 3.000s 104.901us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.672us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.672us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 60.672us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 60.672us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 60.672us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 453.393us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 298.847us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 298.847us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 298.847us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 298.847us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 175.498us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_ctr_fi 2.000s 56.262us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 298.847us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 298.847us 0 1 0.00
aes_control_fi 3.000s 56.950us 1 1 100.00
aes_cipher_fi 3.000s 90.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 44.379us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 19127270972642940413432120078048752875234529977538747039547738712837292922828 930
UVM_INFO @ 228817835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 46436715386797535226161527186203658592161524211434045697322814212048775161177 21567
UVM_INFO @ 1814338551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 87839382851898501948381112907356235995684330173924884254459470258886895878372 20681
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 74560850392599158750304381449210524938788185464677813597531826691796921920124 109
UVM_INFO @ 44379027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---