Simulation Results: aes/unmasked

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.09 %
  • code
  • 88.98 %
  • assert
  • 98.11 %
  • func
  • 74.19 %
  • block
  • 89.36 %
  • line
  • 91.86 %
  • branch
  • 79.42 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 75.689us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 72.967us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 55.576us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 85.305us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 181.632us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 160.463us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 132.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 85.305us 1 1 100.00
aes_csr_aliasing 2.000s 160.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 72.967us 1 1 100.00
aes_config_error 2.000s 74.440us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 72.967us 1 1 100.00
aes_config_error 2.000s 74.440us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_b2b 3.000s 128.058us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 72.967us 1 1 100.00
aes_config_error 2.000s 74.440us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 90.220us 1 1 100.00
aes_config_error 2.000s 74.440us 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 70.906us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 1047.623us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_sideload 3.000s 74.158us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 185.600us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 13.000s 836.216us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 81.316us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 376.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 376.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.576us 1 1 100.00
aes_csr_rw 1.000s 85.305us 1 1 100.00
aes_csr_aliasing 2.000s 160.463us 1 1 100.00
aes_same_csr_outstanding 2.000s 71.731us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.576us 1 1 100.00
aes_csr_rw 1.000s 85.305us 1 1 100.00
aes_csr_aliasing 2.000s 160.463us 1 1 100.00
aes_same_csr_outstanding 2.000s 71.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 157.576us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 170.125us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 20.000s 8059.619us 1 1 100.00
aes_tl_intg_err 2.000s 108.241us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 108.241us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 72.967us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
aes_core_fi 2.000s 76.172us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 74.440us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_core_fi 2.000s 76.172us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.342us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 55.433us 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 96.565us 1 1 100.00
aes_sideload 3.000s 74.158us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 55.433us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 55.433us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 55.433us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 55.433us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 55.433us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 96.565us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.529us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.529us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.529us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 206.529us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 209.015us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_ctr_fi 1.000s 56.335us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 206.529us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 206.529us 0 1 0.00
aes_control_fi 2.000s 52.198us 1 1 100.00
aes_cipher_fi 2.000s 61.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 116.269us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 30149562809530768913370849454421132760185398243914798695032613651970762855672 36061
UVM_INFO @ 836216358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 104798842440114107511049033831955772374192961346256011149769226815407261743509 328
UVM_INFO @ 116269480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 115643013302942314279004895952879374057217785882009737297634499991974238063261 12330
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0