Simulation Results

Simulation Results: chip

10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
73.09 %

code
85.07 %

assert
97.37 %

func
36.82 %

line
94.36 %

branch
93.63 %

cond
88.96 %

toggle
91.28 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.18%
V2S		50.00%
V3		69.23%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	177.320s	2832.463us	1	1	100.00
	chip_sw_example_rom	88.570s	2470.050us	1	1	100.00
	chip_sw_example_manufacturer	123.950s	3030.711us	1	1	100.00
	chip_sw_example_concurrency	152.910s	3427.206us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	180.170s	4270.836us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	363.760s	5067.364us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	243.660s	4497.457us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3128.240s	29462.407us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	58.310s	2195.561us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3128.240s	29462.407us	1	1	100.00
	chip_csr_rw	363.760s	5067.364us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.410s	47.297us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	291.140s	4329.974us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	291.140s	4329.974us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	291.140s	4329.974us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	352.730s	4285.070us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	352.730s	4285.070us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	384.390s	5096.974us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	351.750s	4503.941us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	380.660s	4427.424us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	930.230s	8889.057us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	338.810s	3900.060us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1049.420s	13402.985us	1	1	100.00

209/278 passed

75.18 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	171.920s	4493.049us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	171.920s	4493.049us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	254.600s	4161.646us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	335.190s	5908.832us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	174.170s	3720.562us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	148.920s	3522.864us	1	1	100.00
	chip_tap_straps_testunlock0	235.380s	5202.602us	1	1	100.00
	chip_tap_straps_rma	95.690s	3298.931us	1	1	100.00
	chip_tap_straps_prod	81.500s	3474.177us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	160.960s	3105.864us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	834.610s	9462.298us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	411.050s	6273.256us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	411.050s	6273.256us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	640.390s	8574.208us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	863.590s	9810.784us	0	1	0.00
chip_sw_ast_sys_clk_jitter				9	10	90.00
	chip_sw_flash_ctrl_ops_jitter_en	386.390s	3918.536us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	552.940s	6181.114us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3770.850s	20180.506us	0	1	0.00
	chip_sw_aes_enc_jitter_en	137.730s	2955.896us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	789.630s	7326.679us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	160.580s	3463.897us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1491.300s	11104.360us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.560s	3077.022us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	386.000s	4449.784us	1	1	100.00
	chip_sw_clkmgr_jitter	123.820s	2769.431us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	230.910s	2990.410us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	486.600s	7903.140us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.970s	5681.071us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	140.050s	3027.390us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.970s	5681.071us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	132.710s	2918.000us	1	1	100.00
	chip_sw_aes_smoketest	200.330s	3685.953us	1	1	100.00
	chip_sw_aon_timer_smoketest	203.130s	3535.091us	1	1	100.00
	chip_sw_clkmgr_smoketest	161.810s	3504.089us	1	1	100.00
	chip_sw_csrng_smoketest	168.920s	2842.885us	1	1	100.00
	chip_sw_entropy_src_smoketest	1019.830s	8256.938us	1	1	100.00
	chip_sw_gpio_smoketest	199.170s	2819.920us	1	1	100.00
	chip_sw_hmac_smoketest	202.140s	3331.627us	1	1	100.00
	chip_sw_kmac_smoketest	193.120s	2621.700us	1	1	100.00
	chip_sw_otbn_smoketest	1537.290s	10766.865us	1	1	100.00
	chip_sw_pwrmgr_smoketest	257.430s	6385.194us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	250.070s	6271.051us	1	1	100.00
	chip_sw_rv_plic_smoketest	152.050s	2608.225us	1	1	100.00
	chip_sw_rv_timer_smoketest	185.710s	3173.854us	1	1	100.00
	chip_sw_rstmgr_smoketest	163.670s	3328.618us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	162.510s	3237.671us	1	1	100.00
	chip_sw_uart_smoketest	140.710s	3060.072us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	175.360s	2949.541us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	342.950s	4806.802us	0	1	0.00
chip_sw_boot				0	1	0.00
	chip_sw_uart_tx_rx_bootstrap	7654.130s	63178.630us	0	1	0.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	2822.380s	15038.240us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	67.914s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	214.380s	3345.375us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	219.940s	3025.100us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7327.040s	56065.674us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7830.000s	58510.167us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	55.080s	2032.922us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	55.080s	2032.922us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3128.240s	29462.407us	1	1	100.00
	chip_same_csr_outstanding	3033.440s	29753.463us	1	1	100.00
	chip_csr_hw_reset	180.170s	4270.836us	1	1	100.00
	chip_csr_rw	363.760s	5067.364us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3128.240s	29462.407us	1	1	100.00
	chip_same_csr_outstanding	3033.440s	29753.463us	1	1	100.00
	chip_csr_hw_reset	180.170s	4270.836us	1	1	100.00
	chip_csr_rw	363.760s	5067.364us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	59.000s	2552.122us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.440s	43.237us	1	1	100.00
	xbar_smoke_large_delays	59.880s	10086.074us	1	1	100.00
	xbar_smoke_slow_rsp	46.280s	5162.603us	1	1	100.00
	xbar_random_zero_delays	23.990s	402.525us	1	1	100.00
	xbar_random_large_delays	211.920s	34958.281us	1	1	100.00
	xbar_random_slow_rsp	135.120s	15078.609us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	26.780s	1031.962us	1	1	100.00
	xbar_error_and_unmapped_addr	6.090s	65.233us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	19.970s	903.300us	1	1	100.00
	xbar_error_and_unmapped_addr	6.090s	65.233us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	47.220s	1117.518us	1	1	100.00
	xbar_access_same_device_slow_rsp	172.370s	20650.155us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	28.040s	549.386us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	226.990s	8644.469us	1	1	100.00
	xbar_stress_all_with_error	44.820s	970.410us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	150.970s	1640.989us	1	1	100.00
	xbar_stress_all_with_reset_error	170.080s	3496.643us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	2822.380s	15038.240us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2234.340s	25211.607us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	2775.440s	15926.699us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	86.546s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	14.007s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	8.497s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	64.911s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	28.999s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	86.704s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.481s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	8.994s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.454s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	37.553s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	158.791s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	69.346s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	78.496s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	70.461s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.589s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.910s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	21.640s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	16.650s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.950s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	16.790s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.760s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.870s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.900s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.360s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.320s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.120s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.130s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.850s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.730s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.750s	10.320us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	90.973s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	83.309s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	70.786s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	65.352s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	71.965s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	5648.490s	30532.681us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5835.850s	30459.756us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5689.080s	31120.625us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	2942.890s	16067.845us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3149.670s	35738.705us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3149.670s	35738.705us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	190.810s	3282.661us	1	1	100.00
	chip_sw_aes_enc_jitter_en	137.730s	2955.896us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	181.500s	2765.495us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	151.010s	3007.540us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1573.660s	12252.926us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	176.840s	3412.180us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	341.990s	4719.816us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	564.350s	6186.458us	1	1	100.00
	chip_plic_all_irqs_10	258.700s	3276.164us	1	1	100.00
	chip_plic_all_irqs_20	353.770s	4587.365us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	187.250s	3416.808us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1012.770s	15102.360us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	201.770s	3723.584us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	131.000s	2876.451us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.150s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				0	1	0.00
	chip_sw_alert_handler_lpg_clkoff	876.680s	8067.774us	0	1	0.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	985.630s	8809.453us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	780.760s	8614.406us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8991.190s	254962.569us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	203.730s	3386.284us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	257.430s	6385.194us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	203.730s	3386.284us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	420.610s	7755.259us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	420.610s	7755.259us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	232.360s	6391.479us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	473.280s	6605.433us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	575.710s	5703.553us	1	1	100.00
	chip_sw_aes_idle	151.010s	3007.540us	1	1	100.00
	chip_sw_hmac_enc_idle	190.140s	3409.174us	1	1	100.00
	chip_sw_kmac_idle	216.000s	3730.363us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	254.290s	4633.580us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	302.420s	4731.246us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	288.920s	4199.876us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	306.540s	5114.912us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	907.360s	11388.961us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	408.430s	4141.064us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	355.720s	4684.164us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	360.440s	3876.175us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	392.090s	5348.231us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	428.970s	4755.760us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	368.080s	4340.233us	1	1	100.00
	chip_sw_ast_clk_outputs	640.390s	8574.208us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	659.900s	10996.625us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	360.440s	3876.175us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	392.090s	5348.231us	1	1	100.00
chip_sw_clkmgr_jitter				9	10	90.00
	chip_sw_flash_ctrl_ops_jitter_en	386.390s	3918.536us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	552.940s	6181.114us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3770.850s	20180.506us	0	1	0.00
	chip_sw_aes_enc_jitter_en	137.730s	2955.896us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	789.630s	7326.679us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	160.580s	3463.897us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1491.300s	11104.360us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.560s	3077.022us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	386.000s	4449.784us	1	1	100.00
	chip_sw_clkmgr_jitter	123.820s	2769.431us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	119.720s	3015.480us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	360.550s	4838.051us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	641.630s	8286.398us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3612.310s	25774.099us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	140.190s	3017.881us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	162.660s	3031.629us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1136.780s	11981.417us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	214.700s	3374.576us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	363.050s	5224.337us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1256.750s	20455.219us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2235.990s	20894.414us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	640.390s	8574.208us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	331.930s	4275.688us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	305.540s	4331.700us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				0	1	0.00
	chip_sw_alert_handler_lpg_clkoff	876.680s	8067.774us	0	1	0.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1898.000s	24086.264us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	169.130s	3326.278us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	533.590s	6981.562us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	171.630s	2878.314us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3747.860s	23201.294us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	154.760s	2857.053us	1	1	100.00
	chip_sw_edn_entropy_reqs	569.340s	6292.403us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	154.760s	2857.053us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1898.000s	24086.264us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	180.720s	2749.672us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1020.550s	23131.717us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	538.920s	5942.387us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	552.940s	6181.114us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	363.900s	4018.112us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	386.390s	3918.536us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	2833.620s	43345.064us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1020.550s	23131.717us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	273.550s	4282.979us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	2833.620s	43345.064us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	228.440s	9412.218us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	484.850s	5845.235us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	449.090s	5858.897us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	449.090s	5858.897us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	188.810s	3702.662us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	160.580s	3463.897us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	190.140s	3409.174us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1444.690s	12026.621us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1819.310s	12018.490us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	366.130s	4673.679us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	396.890s	5095.425us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	347.570s	4605.790us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	269.650s	3986.681us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1491.300s	11104.360us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1082.140s	9754.107us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1573.660s	12252.926us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4136.130s	20018.346us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	207.180s	3712.573us	1	1	100.00
	chip_sw_kmac_mode_kmac	169.760s	3177.183us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.560s	3077.022us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	199.420s	3589.186us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1603.120s	11247.472us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	216.000s	3730.363us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	341.990s	4719.816us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	148.920s	3522.864us	1	1	100.00
	chip_tap_straps_rma	95.690s	3298.931us	1	1	100.00
	chip_tap_straps_prod	81.500s	3474.177us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.010s	3276.605us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	755.010s	6928.151us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	147.050s	2915.694us	0	1	0.00
	chip_sw_flash_rma_unlocked	2833.620s	43345.064us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	225.520s	3111.107us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	635.670s	7113.326us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	528.720s	8309.529us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	460.080s	7274.249us	0	1	0.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	267.850s	10081.221us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	626.370s	9107.261us	1	1	100.00
	chip_prim_tl_access	228.440s	9412.218us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	659.900s	10996.625us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	408.430s	4141.064us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	355.720s	4684.164us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	360.440s	3876.175us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	392.090s	5348.231us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	428.970s	4755.760us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	368.080s	4340.233us	1	1	100.00
	chip_tap_straps_dev	148.920s	3522.864us	1	1	100.00
	chip_tap_straps_rma	95.690s	3298.931us	1	1	100.00
	chip_tap_straps_prod	81.500s	3474.177us	1	1	100.00
	chip_rv_dm_lc_disabled	81.810s	4028.339us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	198.560s	4092.052us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	79.350s	3628.056us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	101.920s	3308.866us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	98.410s	3507.745us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1609.200s	33268.881us	1	1	100.00
	chip_rv_dm_lc_disabled	81.810s	4028.339us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	745.400s	12496.072us	0	1	0.00
	chip_sw_lc_walkthrough_prod	568.490s	8426.084us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	870.620s	26204.266us	0	1	0.00
	chip_sw_lc_walkthrough_rma	339.680s	7673.709us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1609.200s	33268.881us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	57.520s	2126.488us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	50.860s	2295.936us	1	1	100.00
	rom_volatile_raw_unlock	65.388s	0.000us	0	1	0.00
chip_sw_otbn_op				1	2	50.00
	chip_sw_otbn_ecdsa_op_irq	3475.430s	17231.990us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3770.850s	20180.506us	0	1	0.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	575.710s	5703.553us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	575.710s	5703.553us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	575.710s	5703.553us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	306.410s	3313.490us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1020.550s	23131.717us	1	1	100.00
	chip_sw_otbn_mem_scramble	306.410s	3313.490us	1	1	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	404.990s	4804.548us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	203.160s	3336.057us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1020.550s	23131.717us	1	1	100.00
	chip_sw_otbn_mem_scramble	306.410s	3313.490us	1	1	100.00
	chip_sw_keymgr_key_derivation	1025.950s	9265.491us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	404.990s	4804.548us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	203.160s	3336.057us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	377.780s	4616.577us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.010s	3276.605us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	225.520s	3111.107us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	635.670s	7113.326us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	528.720s	8309.529us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	460.080s	7274.249us	0	1	0.00
	chip_sw_lc_ctrl_transition	332.470s	6559.409us	1	1	100.00
	chip_prim_tl_access	228.440s	9412.218us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	228.440s	9412.218us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	840.760s	8103.355us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	64.100s	1878.917us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	862.740s	23085.805us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	251.300s	7969.745us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	404.380s	7640.604us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	467.820s	8166.790us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	809.000s	21861.304us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	381.530s	10184.522us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	420.610s	7755.259us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	922.150s	12842.933us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	312.950s	5488.292us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	64.100s	1878.917us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	276.990s	3816.222us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	297.240s	8908.666us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	316.620s	6512.802us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	175.840s	3561.078us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	460.860s	12036.981us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	515.840s	6814.509us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	773.150s	11571.324us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1374.610s	31488.504us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	151.860s	3145.549us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	267.850s	10081.221us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	267.850s	10081.221us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	773.150s	11571.324us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	460.860s	12036.981us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	312.950s	5488.292us	1	1	100.00
	chip_sw_pwrmgr_smoketest	257.430s	6385.194us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	244.140s	3950.419us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	292.260s	5628.776us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	327.040s	5578.764us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1012.770s	15102.360us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	168.420s	3200.372us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	985.630s	8809.453us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	447.330s	5264.556us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	481.310s	4601.935us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	161.730s	2762.871us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	203.160s	3336.057us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	292.260s	5628.776us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	292.260s	5628.776us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1189.780s	16660.309us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	945.440s	13626.154us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	244.140s	3950.419us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	204.520s	2941.827us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	304.320s	6879.428us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	95.690s	3298.931us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	81.810s	4028.339us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	564.350s	6186.458us	1	1	100.00
	chip_plic_all_irqs_10	258.700s	3276.164us	1	1	100.00
	chip_plic_all_irqs_20	353.770s	4587.365us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	170.290s	2539.086us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	163.580s	3157.997us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	2822.380s	15038.240us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	234.630s	3844.392us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	279.060s	4670.931us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	217.030s	3528.401us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	206.820s	2851.695us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	404.990s	4804.548us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	386.000s	4449.784us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	362.090s	7353.900us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	440.810s	7688.704us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	626.370s	9107.261us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
	chip_sw_data_integrity_escalation	411.050s	6273.256us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	515.840s	6814.509us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.790s	23392.600us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	144.580s	2360.082us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	248.690s	3554.944us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	336.340s	4908.403us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.790s	23392.600us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.790s	23392.600us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2174.930s	20487.049us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2174.930s	20487.049us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	355.930s	6510.736us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3149.670s	35738.705us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	126.180s	2947.717us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	160.230s	2706.751us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	289.510s	4172.242us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	365.920s	4264.139us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1047.930s	8607.817us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	4463.690s	31298.932us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1579.560s	12750.524us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	160.730s	2688.620us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	205.140s	3760.833us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	156.440s	3098.030us	0	1	0.00

18/26 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10020.450s	71440.277us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	996.340s	6967.210us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	171.420s	4127.297us	0	1	0.00
	rom_e2e_jtag_debug_dev	194.480s	3635.136us	0	1	0.00
	rom_e2e_jtag_debug_rma	198.510s	4784.744us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	87.540s	3007.219us	0	1	0.00
	rom_e2e_jtag_inject_dev	80.660s	2771.339us	0	1	0.00
	rom_e2e_jtag_inject_rma	217.900s	4692.430us	1	1	100.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	150.868s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	272.460s	3273.663us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	308.010s	3382.552us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	447.200s	4230.840us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	903.580s	7065.242us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	234.130s	2240.330us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	531.060s	4828.381us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	170.480s	3236.972us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	170.790s	2898.656us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	286.240s	6612.997us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	293.260s	4438.974us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	773.150s	11571.324us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	171.420s	4127.297us	0	1	0.00
	rom_e2e_jtag_debug_dev	194.480s	3635.136us	0	1	0.00
	rom_e2e_jtag_debug_rma	198.510s	4784.744us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	408.650s	5306.170us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	490.660s	6523.061us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5630.120s	38746.539us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5630.120s	38746.539us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	144.830s	3478.420us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	352.730s	4285.070us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2975.060s	19311.232us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	234.880s	3611.872us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.320s	10.320us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.130s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	179.400s	3226.469us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	164.750s	3090.660us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	254.390s	4147.584us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.728s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	201.860s	3084.465us	1	1	100.00
	ate_bootstrap_flash_erase	569.280s	10010.340us	0	1	0.00
	ate_bootstrap_one_frame	6625.030s	45276.519us	1	1	100.00
	ate_bootstrap_disjoint	9447.420s	84049.393us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	80709786243978404562808035230979892997315688302374621486768663528116759399863	None	---- STDERR ---- Another command (pid=2082013) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	56095424894577091814408940104247216291623908181929604007898653759486134249264	None	Another command (pid=389161) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=391938) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=501459) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	92755554756083494819564065911827988599349892322921843700804149375305470048588	None	Another command (pid=622635) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=534191) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=640331) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	113101988897386213886111812065878292319258869360985504428818696429226612206768	None	---- STDERR ---- Another command (pid=616623) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=617145) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16998454190330828900588185692641994306800996925609388654561665976750187086912	None	Another command (pid=690061) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=755597) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=732888) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	42945227620798848199537298969616537355681540883789318821934775502889011236964	None	Another command (pid=651832) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=644228) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=664207) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10856673901869705462427929873007956961080095343337847260231616271029265022526	None	Another command (pid=379385) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=386483) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=412998) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	14390263489676045143984786661698126904302177434712682380371344053976435334727	None	Another command (pid=429134) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=622635) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=534191) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	102263761965035170107204371590547585980727385521415064035478159527877105752994	None	---- STDERR ---- Another command (pid=601025) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	9115414269845803855691539665155855423488737284992771649665000458220606998800	None	Another command (pid=612986) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=429134) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=534191) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	113506273960751386752585039803744780185855448591118037581939533293748238663397	None	Another command (pid=615480) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=662583) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=673477) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	50350646985133970255800011912607725817014493239241537239573683819911633954922	None	Another command (pid=388155) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=600477) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=473855) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	57454118296237629074866280882827317554134333826852175171124397250867135160924	None	---- STDERR ---- Another command (pid=603956) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=610389) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	56822699136610673239764244903554163053550710613939281790463622103419152428836	None	Another command (pid=617145) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=630437) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=624847) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	51882295341585611784098006469806050924047103009158255863566448169907602732702	None	---- STDERR ---- Another command (pid=617391) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	48745500413497903821301443201399967724283337037528386058353883237718810080162	None	Another command (pid=602811) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=505368) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=601025) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	39972221891879903554832972138975614431782501099743851083247206554123349717332	None	Another command (pid=379385) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=386483) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=412998) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	53584298679602045297062954678087877392084071220928434491966780023598502788624	None	Another command (pid=504232) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=414810) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=506737) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	8929059339955858271963224723555510873611036233400718325268333212309193041204	None	Another command (pid=473855) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=522501) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=523205) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	12206142588505684164948568574988320881541840383348946627748119425977949037121	None	Another command (pid=414810) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=506737) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=599936) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	33899331248300592423298410880146858134261105058686551560461244337297075648526	None	Another command (pid=385731) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=601636) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=602811) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	76982794341115646156838952451168665761383945020631351037141059546108120321326	None	Another command (pid=391938) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=489926) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=441742) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	5724529829482496297759063897092887239471393326317008781728696997492552500805	None	Another command (pid=379385) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=386483) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=412998) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	69879867271298809659949489283888326356001959083200608027846805251179354953246	None	Another command (pid=388155) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=600477) is running. Waiting for it to complete on the server (server_pid=294529)... Another command (pid=473855) is running. Waiting for it to complete on the server (server_pid=294529)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	36541097004827686036523336076296760065932495742339851691055841816442278336733	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	41079671332082912053281307430776956472322152290141053556738354851037388922782	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	12068686645171771730303445236714134431316088114194201526218471219532049371430	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	105793666740723388447538965617186620302172564717079250716842777757688803877746	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	24898893381955369394814540538637074686816944542590322358117069634881000746976	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	88524492013746086972080990052714158390265934318338350904037556786730837173989	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	85234913226828691204895323102067551816458955205815813780371243155564545047977	378	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	97530832059293637136143119582859169625055244842326674878986531602196182899395	378	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	31185073006935236407473846860480336453209997741964145684103676778424125977062	374	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	72148961097399017036935724446321827854307901024282267621531047304700071657014	338	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	105459969097510396156249641935502892388182756738399826151344483999782695551754	338	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	98003154111954356465853530385864119137974675949509647178410167455550996396507	338	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	51188878153515135882366394935009334913021035772545519465964720214768657524331	349	UVM_ERROR @ 12036.981000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 12036.981000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	40986190847752845141199558232656009486513285040838034249907199997525594736834	332	UVM_ERROR @ 10184.522000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 10184.522000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	53761494276461825043822499525632062134997001223154892619285666932254784787111	325	UVM_ERROR @ 7640.604000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7640.604000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	119565935536331393273892256179356418119576485838329511363230346832069418069	319	UVM_ERROR @ 7755.259000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7755.259000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	chip_sw_lc_walkthrough_prod	35975616817765492092334733134067483519217071322189768230269138539573962115962	None
	chip_sw_otbn_ecdsa_op_irq_jitter_en	1701245557307872362032504966512353940520629676513766115269734117304698688777	None
	chip_sw_alert_handler_lpg_sleep_mode_pings	40323566222239697370731482290716691528153232884137465748102861292172753730057	None
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	45906433169979877400187034199498633907311690588059470256673855115394387630391	310	UVM_INFO @ 12026.620752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	23235088962582712247836270633075360520680555050364468006170624484407529922124	310	UVM_INFO @ 12018.489813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	4358416833272968686146080051238031386977696884454252416109824509261931044757	339	UVM_INFO @ 20018.346344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	29472512803124056386760595961354917168790023784654760929374789861375305782986	328	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13961792232853910379899801742229095955067226237061630428730077752747362203399	333	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	64634520688748887123639668548112138657890505236551847679682188804494404536658	333	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job returned a non-zero exit code: *				2 test runs
	chip_sw_uart_tx_rx_bootstrap	11726314100758242962479626915603243413845707321228017436437690945297249255245	None	Dumping VCS Annotated Stack: Process VmPeak: 818748 kb, VmSize: 818236 kb System Free Memory: 180323096 kb, System Free Swap: 0 kb No context available Command line: /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3237527373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3237527373 make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
	chip_sw_alert_handler_lpg_clkoff	28840649537032096332612240869712535658361290693105304666080120720836839335515	None	Dumping VCS Annotated Stack: Process VmPeak: 802236 kb, VmSize: 801724 kb System Free Memory: 207848472 kb, System Free Swap: 0 kb No context available Command line: /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944498267 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.944498267 make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	42312995964744924272634974926647772198735142305564635215474848389493517549525	316	UVM_ERROR @ 2898.655860 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2898.655860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	83945160795901601069339787903262676120990569347520099443920453833266588365399	312	UVM_ERROR @ 3326.277990 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3326.277990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				2 test runs
	chip_sw_lc_walkthrough_dev	40695264178518429103908306691172577774826028886369582808495974738008393328497	369	UVM_INFO @ 12496.072398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	45214967407381491461143453667978912367221720128107702502752868953129629891463	343	UVM_INFO @ 7673.708619 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	73551314334700271810165937940530877465627053844435255423473507470720773813964	313	UVM_ERROR @ 3561.078352 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3561.078352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	5045035074642482050153324708566718599724266888569496467654680601094911684286	332	UVM_ERROR @ 8908.665784 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 8908.665784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	97116378330066412655393943639824138529647577796647776355298581891530156785802	217	TL item was: req: (cip_tl_seq_item@34774) { a_addr: 'h10428 a_data: 'ha1d7aa1b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h199ab d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2032.921996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	77442866453622357784771416881455600819802695094752126197374237469803769236942	229	TL item was: req: (cip_tl_seq_item@32014) { a_addr: 'h10400 a_data: 'h4666c2ab a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h195ab d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2195.561397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	104721991526699986043544439923838911645114401815484329320655345457091755311609	366	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	28148587367992289844570765522516265482554232963534225203558678309239140578907	325	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	105847489261417334660054232746371927102590613737154083625867504767544955941778	368	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	108885004902909058104494510794489037625824675350405367857233996597821960399576	336	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	98381058355450980693071054056217145550943256682499686266259142546165932075205	301	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	38361365301924767223179421747844611251792079466222137965433894143965409275807	329	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	61583985152788572837931658248944997950342678858837389619556162839779745523471	309	UVM_INFO @ 2915.694140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	10337202613493340977050504558226879942165675651297124079917451401092062925671	342	UVM_INFO @ 7274.249223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	2172002684559089127818583004811453339129404037229254858757112664496342589358	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_prodend	37593773556815857600346128145057366852943748807245240632091223171833537074222	308	UVM_INFO @ 26204.265536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	36924567507799836642717586212364945834129158508190350992087314509444908070598	303	UVM_ERROR @ 1878.917260 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 1878.917260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	89474174858489645653734622517807385660284356141062389076800213250915534463239	337	UVM_INFO @ 35738.705466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	83577383367347586355447199689324028899321389852181121019689892260307104691664	307	UVM_INFO @ 3412.179810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	33861050296395932321277274039496750896838916090937884049444442351749349317963	308	UVM_INFO @ 2876.450740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	114486232894526331848291376364451109880667211127994791913330857592698738654756	343	UVM_INFO @ 3273.663350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	76453574697482370248541723875499115537996097610618490246687828675807142669837	230	UVM_INFO @ 4028.338845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	7353751046035259619972193038546568293290776705368622764094557986709322622877	327	UVM_INFO @ 3098.029739 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	101540159187522809279809602810073545387783212929590030934111765052131702848958	312	UVM_INFO @ 3345.375000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	483871272574098113694674963730255786531363877842126390025275605061992195706	318	UVM_INFO @ 3025.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	50992703559169295038605519096719132615199819651308047670937640533262552886609	332	UVM_INFO @ 9810.784354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	70978859222815239929298643886424327224851819799335362043214362348934390402874	277	UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	98095825308864692146322338034061623121340381868767797205529192636836455526248	325	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	55539875343456445576463477211420108588176439589614736148128192712488071183085	335	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	80131161869727902360238802468701731713783234881016083562478555238823324295026	327	UVM_ERROR @ 4806.801744 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4806.801744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---