Simulation Results: clkmgr

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.14 %
  • code
  • 98.26 %
  • assert
  • 95.06 %
  • func
  • 86.11 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 93.24 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.070s 26.368us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 25.131us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.580s 214.103us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.090s 74.587us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 38.752us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
clkmgr_csr_aliasing 2.090s 74.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.940s 48.446us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.830s 33.157us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.920s 106.072us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.890s 27.390us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.070s 26.368us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.710s 2236.374us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.100s 169.900us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.710s 2236.374us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 14.780s 4960.848us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.720s 17.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.440s 58.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.440s 58.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 25.131us 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
clkmgr_csr_aliasing 2.090s 74.587us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 23.509us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 25.131us 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
clkmgr_csr_aliasing 2.090s 74.587us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 23.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 2.080s 542.144us 1 1 100.00
clkmgr_tl_intg_err 1.570s 143.159us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 564.220s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 564.220s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 564.220s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 564.220s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.020s 453.424us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.570s 143.159us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.710s 2236.374us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.100s 169.900us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 564.220s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.860s 79.036us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.030s 128.479us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 23.773us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.030s 26.388us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.730s 50.193us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.080s 542.144us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.700s 16.612us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.080s 542.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.940s 1544.452us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 33.650s 3228.058us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 89122085229125023243199694665046236681712699510206067645581608068232102281884 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---