Simulation Results: csrng

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.97 %
  • code
  • 92.11 %
  • assert
  • 93.89 %
  • func
  • 74.91 %
  • block
  • 96.82 %
  • line
  • 97.55 %
  • branch
  • 92.09 %
  • toggle
  • 93.10 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 79.163us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 32.191us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.091us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 35.000s 3727.870us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 87.108us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 108.145us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.091us 1 1 100.00
csrng_csr_aliasing 5.000s 87.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 648.460us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 54.332us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 54.332us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 659.000s 72197.930us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 20.885us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 102.643us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 20.636us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 20.636us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 32.191us 1 1 100.00
csrng_csr_rw 2.000s 15.091us 1 1 100.00
csrng_csr_aliasing 5.000s 87.108us 1 1 100.00
csrng_same_csr_outstanding 3.000s 124.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 32.191us 1 1 100.00
csrng_csr_rw 2.000s 15.091us 1 1 100.00
csrng_csr_aliasing 5.000s 87.108us 1 1 100.00
csrng_same_csr_outstanding 3.000s 124.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
csrng_tl_intg_err 4.000s 140.224us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 53.954us 1 1 100.00
csrng_csr_rw 2.000s 15.091us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 648.460us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 659.000s 72197.930us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 648.460us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 659.000s 72197.930us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 648.460us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 140.224us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
csrng_sec_cm 3.000s 75.939us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 116.815us 1 1 100.00
csrng_err 3.000s 79.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 33.000s 878.517us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 61755338052416281220485497902562322432197098834332647188105136676193007700583 100
UVM_INFO @ 54332248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 57237031608402949323354315400559234524965000421291825253533406318740912810377 146
UVM_INFO @ 878516650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---