Simulation Results: edn/edn0

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.53 %
  • code
  • 78.61 %
  • assert
  • 95.01 %
  • func
  • 79.96 %
  • line
  • 96.85 %
  • branch
  • 89.40 %
  • cond
  • 83.92 %
  • toggle
  • 75.59 %
  • FSM
  • 47.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 23.654us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 18.940us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 21.902us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.370s 434.441us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.380s 164.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 77.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 21.902us 1 1 100.00
edn_csr_aliasing 1.380s 164.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 36.752us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 36.752us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 36.752us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.890s 49.873us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 43.013us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 321.437us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 57.791us 1 1 100.00
edn_disable_auto_req_mode 1.200s 30.376us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.340s 107.212us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 40.319us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.080s 30.901us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 141.046us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 141.046us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 18.940us 1 1 100.00
edn_csr_rw 0.860s 21.902us 1 1 100.00
edn_csr_aliasing 1.380s 164.347us 1 1 100.00
edn_same_csr_outstanding 1.110s 130.745us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 18.940us 1 1 100.00
edn_csr_rw 0.860s 21.902us 1 1 100.00
edn_csr_aliasing 1.380s 164.347us 1 1 100.00
edn_same_csr_outstanding 1.110s 130.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
edn_tl_intg_err 1.670s 624.112us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.960s 16.455us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 43.013us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 43.013us 1 1 100.00
edn_sec_cm 4.450s 1161.183us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 43.013us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.670s 624.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.000s 2887.445us 1 1 100.00