Simulation Results: edn/edn1

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.51 %
  • code
  • 82.15 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 89.92 %
  • toggle
  • 87.74 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 17.474us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 87.264us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 27.364us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.600s 542.875us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.220s 37.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.150s 64.178us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 27.364us 1 1 100.00
edn_csr_aliasing 1.220s 37.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.940s 30.605us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.940s 30.605us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.940s 30.605us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 23.072us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.950s 86.068us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 18.121us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 11.117us 1 1 100.00
edn_disable_auto_req_mode 1.010s 42.475us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.910s 54.237us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 39.827us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 16.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.970s 183.636us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.970s 183.636us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 87.264us 1 1 100.00
edn_csr_rw 0.740s 27.364us 1 1 100.00
edn_csr_aliasing 1.220s 37.183us 1 1 100.00
edn_same_csr_outstanding 0.810s 59.828us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 87.264us 1 1 100.00
edn_csr_rw 0.740s 27.364us 1 1 100.00
edn_csr_aliasing 1.220s 37.183us 1 1 100.00
edn_same_csr_outstanding 0.810s 59.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
edn_tl_intg_err 3.130s 144.935us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.710s 46.138us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.950s 86.068us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.950s 86.068us 1 1 100.00
edn_sec_cm 4.150s 372.170us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.950s 86.068us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.130s 144.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 54.860s 13972.905us 1 1 100.00