Simulation Results: entropy_src/rng_4bits

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.97 %
  • code
  • 88.99 %
  • assert
  • 84.89 %
  • func
  • 54.04 %
  • block
  • 94.56 %
  • line
  • 97.24 %
  • branch
  • 86.86 %
  • toggle
  • 76.02 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 188.732us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 53.810us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 116.965us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 1042.399us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 183.556us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 51.781us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 116.965us 1 1 100.00
entropy_src_csr_aliasing 4.000s 183.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 188.732us 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
entropy_src_fw_ov 53.000s 14144.271us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 53.000s 14144.271us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 300.000s 13052.836us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
entropy_src_intr 2.000s 46.520us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
entropy_src_functional_alerts 4.000s 682.212us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 51.000s 13106.813us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 29.545us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 299.767us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 34.407us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 379.094us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 379.094us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 53.810us 1 1 100.00
entropy_src_csr_rw 2.000s 116.965us 1 1 100.00
entropy_src_csr_aliasing 4.000s 183.556us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 36.248us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 53.810us 1 1 100.00
entropy_src_csr_rw 2.000s 116.965us 1 1 100.00
entropy_src_csr_aliasing 4.000s 183.556us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 36.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 97.688us 1 1 100.00
entropy_src_tl_intg_err 3.000s 340.850us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
entropy_src_cfg_regwen 2.000s 44.606us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
entropy_src_fw_ov 53.000s 14144.271us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
entropy_src_sec_cm 2.000s 97.688us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
entropy_src_sec_cm 2.000s 97.688us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 14.000s 14301.848us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
entropy_src_sec_cm 2.000s 97.688us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
entropy_src_sec_cm 2.000s 97.688us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 52.443us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 682.212us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 340.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 231.000s 14016.799us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 19.000s 3519.841us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 50588257746648619985985677238989463950893545729445004454644439621296512178325 738
UVM_INFO @ 3519841269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror markov_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 58839845589738141996914831323305221004838507463161757866203895929740887860058 113
UVM_INFO @ 51780523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---