Simulation Results: flash_ctrl

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 94.44 %
  • assert
  • 96.93 %
  • func
  • 95.85 %
  • line
  • 95.99 %
  • branch
  • 97.16 %
  • cond
  • 94.15 %
  • toggle
  • 97.84 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 97.480s 88.689us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.870s 27.024us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 21.630s 95.907us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 37.460s 2531.183us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 39.780s 2801.291us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.100s 66.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
flash_ctrl_csr_aliasing 39.780s 2801.291us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.950s 17.407us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.310s 19.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.580s 102.097us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 29.720s 226.258us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1172.790s 342725.979us 1 1 100.00
flash_ctrl_hw_rma_reset 616.730s 160181.010us 1 1 100.00
flash_ctrl_lcmgr_intg 5.960s 59.771us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1237.140s 392868.796us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 180.400s 8195.616us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 103.870s 4431.170us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2672.580s 86087.822us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 148.610s 8040.003us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.330s 33.526us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.930s 40.169us 1 1 100.00
flash_ctrl_re_evict 16.340s 546.492us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 86.470s 52.927us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 86.470s 52.927us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 269.730s 64032.655us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.680s 91.658us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 292.540s 987.043us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 351.630s 6743.888us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 347.410s 3258.243us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 901.160s 1004.355us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.210s 155.947us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 116.450s 1983.731us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.400s 133.273us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.490s 17.023us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 15.060s 106.671us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 73.260s 1735.912us 1 1 100.00
flash_ctrl_otp_reset 44.090s 602.480us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1172.790s 342725.979us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 192.850s 3477.409us 1 1 100.00
flash_ctrl_intr_wr 3603.866s 0.000us 0 1 0.00
flash_ctrl_intr_rd_slow_flash 76.920s 5922.343us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 155.990s 26932.297us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 52.070s 3486.415us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 41.700s 646.724us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.590s 62.248us 1 1 100.00
flash_ctrl_ro_derr 94.290s 2792.108us 1 1 100.00
flash_ctrl_rw_derr 132.320s 1433.603us 1 1 100.00
flash_ctrl_derr_detect 109.290s 2459.974us 1 1 100.00
flash_ctrl_integrity 489.490s 10516.646us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.520s 84.791us 1 1 100.00
flash_ctrl_ro_serr 102.120s 1611.814us 1 1 100.00
flash_ctrl_rw_serr 115.010s 2472.288us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 47.010s 2548.887us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 53.740s 3095.539us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 149.040s 2795.137us 1 1 100.00
flash_ctrl_write_word_sweep 7.300s 155.476us 1 1 100.00
flash_ctrl_read_word_sweep 6.780s 87.659us 1 1 100.00
flash_ctrl_ro 80.510s 2222.661us 1 1 100.00
flash_ctrl_rw 356.140s 15244.986us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 26.800s 344.241us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 611.580s 167886.277us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 50.710s 10034.844us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.830s 68.795us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.890s 53.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.630s 231.056us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.630s 231.056us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.630s 95.907us 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
flash_ctrl_csr_aliasing 39.780s 2801.291us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.150s 135.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.630s 95.907us 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
flash_ctrl_csr_aliasing 39.780s 2801.291us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.150s 135.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 38.030s 510.448us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
flash_ctrl_tl_intg_err 390.760s 2198.099us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 390.760s 2198.099us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 390.760s 2198.099us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.640s 221.109us 1 1 100.00
flash_ctrl_wr_intg 7.170s 45.279us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 97.480s 88.689us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 44.090s 602.480us 1 1 100.00
flash_ctrl_disable 10.400s 133.273us 1 1 100.00
flash_ctrl_sec_info_access 45.570s 13649.779us 1 1 100.00
flash_ctrl_connect 7.490s 17.023us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.200s 58.186us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.420s 307.312us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.170s 34.702us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.400s 133.273us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.640s 221.109us 1 1 100.00
flash_ctrl_access_after_disable 6.080s 39.236us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.520s 56.229us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.400s 133.273us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.680s 91.658us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 356.140s 15244.986us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 115.010s 2472.288us 1 1 100.00
flash_ctrl_rw_derr 132.320s 1433.603us 1 1 100.00
flash_ctrl_integrity 489.490s 10516.646us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1172.790s 342725.979us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.600s 899.563us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.360s 21.504us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.330s 81.263us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1626.040s 3290.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.830s 359.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 77.090s 191.184us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_intr_wr 82655399678940684959944620643148003505862085413286863317146895084855114097153 None