Simulation Results: hmac

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.23 %
  • code
  • 97.96 %
  • assert
  • 98.46 %
  • func
  • 44.28 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.140s 891.695us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.710s 59.271us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.890s 111.719us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.360s 218.092us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.340s 58.440us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.050s 165.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.890s 111.719us 1 1 100.00
hmac_csr_aliasing 2.340s 58.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.720s 4466.800us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 70.050s 1691.950us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 242.830s 32849.812us 1 1 100.00
hmac_test_sha384_vectors 373.270s 50233.457us 1 1 100.00
hmac_test_sha512_vectors 341.490s 11521.720us 1 1 100.00
hmac_test_hmac256_vectors 7.110s 462.334us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 1603.170us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1451.545us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 26.450s 2664.303us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 959.520s 52542.772us 1 1 100.00
error 1 1 100.00
hmac_error 13.560s 1350.371us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 15.760s 2176.478us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.140s 891.695us 1 1 100.00
hmac_long_msg 36.720s 4466.800us 1 1 100.00
hmac_back_pressure 70.050s 1691.950us 1 1 100.00
hmac_datapath_stress 959.520s 52542.772us 1 1 100.00
hmac_burst_wr 26.450s 2664.303us 1 1 100.00
hmac_stress_all 141.220s 35656.817us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.140s 891.695us 1 1 100.00
hmac_long_msg 36.720s 4466.800us 1 1 100.00
hmac_back_pressure 70.050s 1691.950us 1 1 100.00
hmac_datapath_stress 959.520s 52542.772us 1 1 100.00
hmac_wipe_secret 15.760s 2176.478us 1 1 100.00
hmac_test_sha256_vectors 242.830s 32849.812us 1 1 100.00
hmac_test_sha384_vectors 373.270s 50233.457us 1 1 100.00
hmac_test_sha512_vectors 341.490s 11521.720us 1 1 100.00
hmac_test_hmac256_vectors 7.110s 462.334us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 1603.170us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1451.545us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.140s 891.695us 1 1 100.00
hmac_long_msg 36.720s 4466.800us 1 1 100.00
hmac_back_pressure 70.050s 1691.950us 1 1 100.00
hmac_datapath_stress 959.520s 52542.772us 1 1 100.00
hmac_burst_wr 26.450s 2664.303us 1 1 100.00
hmac_error 13.560s 1350.371us 1 1 100.00
hmac_wipe_secret 15.760s 2176.478us 1 1 100.00
hmac_test_sha256_vectors 242.830s 32849.812us 1 1 100.00
hmac_test_sha384_vectors 373.270s 50233.457us 1 1 100.00
hmac_test_sha512_vectors 341.490s 11521.720us 1 1 100.00
hmac_test_hmac256_vectors 7.110s 462.334us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 1603.170us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1451.545us 1 1 100.00
hmac_stress_all 141.220s 35656.817us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 141.220s 35656.817us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 21.999us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 17.725us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.590s 566.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.590s 566.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.710s 59.271us 1 1 100.00
hmac_csr_rw 0.890s 111.719us 1 1 100.00
hmac_csr_aliasing 2.340s 58.440us 1 1 100.00
hmac_same_csr_outstanding 1.580s 48.349us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.710s 59.271us 1 1 100.00
hmac_csr_rw 0.890s 111.719us 1 1 100.00
hmac_csr_aliasing 2.340s 58.440us 1 1 100.00
hmac_same_csr_outstanding 1.580s 48.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 143.318us 1 1 100.00
hmac_tl_intg_err 2.470s 676.123us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.470s 676.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.140s 891.695us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.110s 50.692us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 26.890s 2183.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.990s 199.880us 1 1 100.00