Simulation Results

Simulation Results: i2c

10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
88.06 %

code
81.73 %

assert
97.25 %

func
85.20 %

line
96.57 %

branch
92.62 %

cond
86.92 %

toggle
89.66 %

FSM
42.86 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	14.460s	2656.181us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.260s	866.856us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.760s	48.718us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.850s	19.146us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.170s	5077.157us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.220s	27.493us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	22.296us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.850s	19.146us	1	1	100.00
	i2c_csr_aliasing	1.220s	27.493us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.890s	9.942us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	1162.830s	35259.836us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	6.770s	3073.578us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.800s	30.899us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	46.370s	3566.456us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	49.840s	20048.651us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.930s	160.733us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.270s	394.926us	1	1	100.00
	i2c_host_fifo_reset_rx	7.570s	267.089us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	89.660s	9010.733us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.170s	2029.153us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.640s	11.599us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.970s	494.372us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	72.180s	41717.449us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.960s	559.254us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.720s	5527.202us	1	1	100.00
	i2c_target_intr_smoke	4.690s	10903.954us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.230s	434.207us	1	1	100.00
	i2c_target_fifo_reset_tx	1.110s	214.046us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	6.850s	10323.924us	1	1	100.00
	i2c_target_stress_rd	11.720s	5527.202us	1	1	100.00
	i2c_target_intr_stress_wr	44.140s	23695.003us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.320s	7791.927us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	4.030s	10044.773us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.460s	1522.197us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.840s	2550.846us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.680s	855.153us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.320s	691.535us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	6.770s	3073.578us	1	1	100.00
	i2c_host_perf_precise	5.660s	2539.399us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.170s	2029.153us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.190s	127.911us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.500s	1857.906us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.840s	2219.309us	1	1	100.00
	i2c_target_nack_txstretch	1.220s	178.822us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.520s	2106.095us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.530s	461.085us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.680s	37.045us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.700s	24.601us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.400s	98.435us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.400s	98.435us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	48.718us	1	1	100.00
	i2c_csr_rw	0.850s	19.146us	1	1	100.00
	i2c_csr_aliasing	1.220s	27.493us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	67.632us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	48.718us	1	1	100.00
	i2c_csr_rw	0.850s	19.146us	1	1	100.00
	i2c_csr_aliasing	1.220s	27.493us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	67.632us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.270s	89.050us	1	1	100.00
	i2c_sec_cm	1.040s	61.385us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.270s	89.050us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.050s	775.676us	1
target_error_intr				1
	i2c_target_unexp_stop	1.160s	329.773us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	11.360s	980.803us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	7330055728480136502154602523506744623174312925526806387091187357818023774832	88	UVM_INFO @ 9941821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	93432122912308739243047093430325712657085155089198075905418371686093475891912	81	UVM_INFO @ 11599280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	65278361788152036916899849174774854846052284024391943029864253462161196897653	89	UVM_INFO @ 775675792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	81356513830004347669368793335864535736538727123639084120509775331255067902533	96	UVM_INFO @ 980803468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	77128634891452680140942392331027359055824626364252036040879831093190811310368	84	UVM_INFO @ 494371868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	41457156994700014344889807607847081728270140210836208583620873590414009368544	78	UVM_INFO @ 10044772966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	75367127961430268781137340269013029287887053277325832229665334580927784689700	78	UVM_INFO @ 329773353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	51367414588582292714730237285551657991874973133850884463222188780157875834390	78	UVM_INFO @ 178822446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---