Simulation Results: keymgr

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.36 %
  • code
  • 94.08 %
  • assert
  • 97.49 %
  • func
  • 64.51 %
  • line
  • 98.60 %
  • branch
  • 97.26 %
  • cond
  • 93.52 %
  • toggle
  • 97.32 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 21.660s 4735.606us 1 1 100.00
random 1 1 100.00
keymgr_random 5.210s 790.792us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.340s 38.756us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 12.670s 24458.012us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.990s 126.512us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.980s 202.211us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
keymgr_csr_aliasing 5.990s 126.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 6.260s 674.590us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.010s 177.921us 1 1 100.00
keymgr_sideload_kmac 5.550s 348.735us 1 1 100.00
keymgr_sideload_aes 3.070s 175.779us 1 1 100.00
keymgr_sideload_otbn 4.790s 590.343us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.780s 919.735us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.460s 29.600us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.840s 102.671us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.090s 1328.591us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 9.960s 1403.738us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.400s 93.572us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 24.220s 1112.140us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.770s 29.773us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.730s 54.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.150s 325.459us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.150s 325.459us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.340s 38.756us 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
keymgr_csr_aliasing 5.990s 126.512us 1 1 100.00
keymgr_same_csr_outstanding 2.380s 106.811us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.340s 38.756us 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
keymgr_csr_aliasing 5.990s 126.512us 1 1 100.00
keymgr_same_csr_outstanding 2.380s 106.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
keymgr_tl_intg_err 5.590s 551.163us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.210s 233.095us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.210s 233.095us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.210s 233.095us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.210s 233.095us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 5.880s 655.931us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.590s 551.163us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.210s 233.095us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 6.260s 674.590us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 5.210s 790.792us 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 5.210s 790.792us 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 5.210s 790.792us 1 1 100.00
keymgr_csr_rw 1.110s 46.091us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.460s 29.600us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 9.960s 1403.738us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 9.960s 1403.738us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 5.210s 790.792us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.100s 68.684us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 5.900s 196.389us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.460s 29.600us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.900s 196.389us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.900s 196.389us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.900s 196.389us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.850s 583.473us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 5.900s 196.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 1.820s 511.753us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 7420997091967032482861957011662544114383256687760582373552343480567128422643 154
UVM_INFO @ 511753216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---