Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 83.92 %
  • assert
  • 94.69 %
  • func
  • 91.99 %
  • line
  • 97.15 %
  • branch
  • 93.70 %
  • cond
  • 79.36 %
  • toggle
  • 85.83 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.060s 186.638us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 103.960us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.110s 26.774us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 105.205us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 26.002us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.350s 21.902us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.110s 26.774us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 26.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.480s 160.313us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.020s 203.071us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 13.625us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.740s 135.291us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.650s 453.556us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_prog_failure 1.740s 135.291us 1 1 100.00
lc_ctrl_errors 5.650s 453.556us 1 1 100.00
lc_ctrl_security_escalation 6.290s 9049.303us 1 1 100.00
lc_ctrl_jtag_state_failure 23.430s 8070.791us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.100s 429.104us 1 1 100.00
lc_ctrl_jtag_errors 5.580s 458.476us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.430s 180.124us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.080s 1297.869us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.100s 429.104us 1 1 100.00
lc_ctrl_jtag_errors 5.580s 458.476us 0 1 0.00
lc_ctrl_jtag_access 2.330s 218.917us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.810s 1402.627us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.700s 1194.882us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.140s 287.389us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.680s 3478.062us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.930s 1253.337us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.480s 43.092us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.340s 283.571us 1 1 100.00
lc_ctrl_jtag_alert_test 1.050s 58.855us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.500s 264.387us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 14.815us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 10.490s 3829.745us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 84.443us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.790s 88.749us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.790s 88.749us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 103.960us 1 1 100.00
lc_ctrl_csr_rw 1.110s 26.774us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 26.002us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 23.375us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 103.960us 1 1 100.00
lc_ctrl_csr_rw 1.110s 26.774us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 26.002us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 23.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
lc_ctrl_tl_intg_err 1.420s 189.026us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.420s 189.026us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.020s 203.071us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.780s 5664.230us 1 1 100.00
lc_ctrl_sec_cm 7.500s 454.336us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.290s 9049.303us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.480s 160.313us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.080s 1297.869us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.300s 444.115us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.300s 444.115us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.300s 631.738us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.070s 622.117us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.070s 622.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 58.760s 2843.184us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 50968031125547170186004082092240472745606758540460207109566073467423797082774 704
UVM_INFO @ 458476263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 107497791057484373546627630851363372370975003951572713442333520265547498486633 10241
UVM_INFO @ 2843184275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---