Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.93 %
  • code
  • 84.04 %
  • assert
  • 94.97 %
  • func
  • 93.77 %
  • line
  • 97.04 %
  • branch
  • 93.37 %
  • cond
  • 79.54 %
  • toggle
  • 87.62 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.940s 75.255us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 18.047us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.063us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.670s 562.366us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.611us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.010s 32.612us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 44.063us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.800s 405.385us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.980s 692.147us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 42.958us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.140s 353.855us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.070s 845.891us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_prog_failure 2.140s 353.855us 1 1 100.00
lc_ctrl_errors 4.070s 845.891us 1 1 100.00
lc_ctrl_security_escalation 4.200s 327.848us 1 1 100.00
lc_ctrl_jtag_state_failure 29.560s 5427.447us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.990s 192.350us 1 1 100.00
lc_ctrl_jtag_errors 70.390s 15467.155us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.070s 581.889us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.170s 1965.506us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.990s 192.350us 1 1 100.00
lc_ctrl_jtag_errors 70.390s 15467.155us 1 1 100.00
lc_ctrl_jtag_access 2.130s 904.534us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.400s 3139.586us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.830s 229.054us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.380s 631.201us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 17.050s 1074.362us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.720s 4908.141us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.910s 22.831us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.530s 418.983us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 56.275us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.760s 2435.859us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 49.020us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 63.420s 6367.401us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.060s 24.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.740s 261.454us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.740s 261.454us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 18.047us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.063us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.611us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 72.044us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 18.047us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.063us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.611us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 72.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 264.469us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 264.469us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.980s 692.147us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.980s 498.069us 1 1 100.00
lc_ctrl_sec_cm 6.330s 1315.844us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.200s 327.848us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.800s 405.385us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.170s 1965.506us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.320s 415.168us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.320s 415.168us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.770s 337.154us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.970s 3734.745us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.970s 3734.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.250s 1758.096us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 115155978685789000501904370357617586988590337939984267899264392526092525166461 847
UVM_INFO @ 1758096430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---