Simulation Results: otbn

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.48 %
  • code
  • 94.27 %
  • assert
  • 90.43 %
  • func
  • 98.73 %
  • block
  • 99.34 %
  • line
  • 99.51 %
  • branch
  • 91.73 %
  • toggle
  • 88.27 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 40.697us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 37.000s 18.269us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 35.000s 21.674us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 40.000s 137.584us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 49.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 69.638us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 35.000s 21.674us 1 1 100.00
otbn_csr_aliasing 37.000s 49.975us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 45.000s 509.125us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 22.000s 4668.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 21.000s 312.816us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 46.000s 194.038us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 8.000s 33.245us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 63.000s 244.791us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 28.000s 16.210us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 93.315us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 43.412us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 37.000s 51.651us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 23.673us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 96.544us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 96.544us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 37.000s 18.269us 1 1 100.00
otbn_csr_rw 35.000s 21.674us 1 1 100.00
otbn_csr_aliasing 37.000s 49.975us 1 1 100.00
otbn_same_csr_outstanding 4.000s 145.229us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 37.000s 18.269us 1 1 100.00
otbn_csr_rw 35.000s 21.674us 1 1 100.00
otbn_csr_aliasing 37.000s 49.975us 1 1 100.00
otbn_same_csr_outstanding 4.000s 145.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 16.000s 55.464us 1 1 100.00
otbn_dmem_err 32.000s 13.626us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 39.000s 205.586us 1 1 100.00
otbn_controller_ispr_rdata_err 40.000s 15.081us 1 1 100.00
otbn_mac_bignum_acc_err 5.000s 29.560us 1 1 100.00
otbn_urnd_err 4.000s 10.904us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 25.000s 18.304us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 96.592us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 24.122us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
otbn_tl_intg_err 16.000s 210.914us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 40.000s 180.348us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 40.697us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 32.000s 13.626us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 16.000s 55.464us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 210.914us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 16.210us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 55.464us 1 1 100.00
otbn_dmem_err 32.000s 13.626us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 93.315us 1 1 100.00
otbn_illegal_mem_acc 25.000s 18.304us 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 55.464us 1 1 100.00
otbn_dmem_err 32.000s 13.626us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 93.315us 1 1 100.00
otbn_illegal_mem_acc 25.000s 18.304us 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 16.210us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 55.464us 1 1 100.00
otbn_dmem_err 32.000s 13.626us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 93.315us 1 1 100.00
otbn_illegal_mem_acc 25.000s 18.304us 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 36.000s 68.811us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 25.808us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 46.000s 215.670us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 46.000s 215.670us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 20.608us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 123.642us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 16.963us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 16.963us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 13.000s 88.938us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 8.000s 33.245us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 292.761us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 56.287us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 1330.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 120.000s 3109.103us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 72.231us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 115235782239722547515980037619182601301396831245171449907373696241503432735369 150
UVM_INFO @ 33244621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 95905413117380564569424367697656471037951500807735157414126181550746447643647 253
UVM_INFO @ 3109103344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---