Simulation Results: otp_ctrl

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.83 %
  • code
  • 79.48 %
  • assert
  • 94.88 %
  • func
  • 77.12 %
  • line
  • 88.62 %
  • branch
  • 83.59 %
  • cond
  • 90.38 %
  • toggle
  • 89.49 %
  • FSM
  • 45.31 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.080s 831.848us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.910s 102.108us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.460s 40.512us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.680s 125.591us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.600s 210.640us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.230s 1693.540us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.460s 40.512us 1 1 100.00
otp_ctrl_csr_aliasing 4.600s 210.640us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.100s 39.307us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 565.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.130s 1277.311us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.360s 180.865us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 18.410s 5514.717us 1 1 100.00
otp_ctrl_check_fail 12.900s 7757.441us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.490s 524.664us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 11.580s 803.792us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.650s 1535.813us 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.010s 963.093us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 17.040s 981.642us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 23.530s 10015.076us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 137.190s 10556.790us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.220s 46.193us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.730s 108.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.550s 625.388us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.550s 625.388us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 102.108us 1 1 100.00
otp_ctrl_csr_rw 1.460s 40.512us 1 1 100.00
otp_ctrl_csr_aliasing 4.600s 210.640us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.000s 184.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 102.108us 1 1 100.00
otp_ctrl_csr_rw 1.460s 40.512us 1 1 100.00
otp_ctrl_csr_aliasing 4.600s 210.640us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.000s 184.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
otp_ctrl_tl_intg_err 14.800s 4806.250us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.800s 4806.250us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_macro_errs 17.040s 981.642us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_macro_errs 17.040s 981.642us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 535.196us 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.360s 180.865us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 12.900s 7757.441us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.790s 912.003us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 136.830s 44597.796us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.490s 524.664us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.590s 190.271us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 17.040s 981.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.860s 7556.636us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 52.010s 33442.944us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_test_access_vseq] wait timeout occurred! 1 test run
otp_ctrl_test_access 67254707808354087480087195232957618812185759001329434100992392489385326950712 89
UVM_INFO @ 10015075960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 14460972176808140859951535304927140964037384076996593111209002176494662409182 10996
UVM_INFO @ 33442943826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---