Simulation Results: pwm

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.04 %
  • code
  • 96.24 %
  • assert
  • 99.20 %
  • func
  • 98.68 %
  • block
  • 99.12 %
  • line
  • 99.40 %
  • branch
  • 98.46 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 3.000s 1594.937us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 51.641us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 2.000s 15.642us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 4.000s 648.405us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 60.322us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 1.000s 127.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 2.000s 15.642us 1 1 100.00
pwm_csr_aliasing 2.000s 60.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
pwm_phase 32.000s 10830.202us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 30.000s 10507.637us 1 1 100.00
perf 1 1 100.00
pwm_perf 26.000s 28376.204us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 60.000s 7247.868us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 110.000s 295665.907us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 23.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 2.000s 247.178us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 2.000s 247.178us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 51.641us 1 1 100.00
pwm_csr_rw 2.000s 15.642us 1 1 100.00
pwm_csr_aliasing 2.000s 60.322us 1 1 100.00
pwm_same_csr_outstanding 1.000s 73.782us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 51.641us 1 1 100.00
pwm_csr_rw 2.000s 15.642us 1 1 100.00
pwm_csr_aliasing 2.000s 60.322us 1 1 100.00
pwm_same_csr_outstanding 1.000s 73.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_tl_intg_err 2.000s 134.655us 1 1 100.00
pwm_sec_cm 1.000s 55.035us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 2.000s 134.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 33.000s 10945.016us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.pwm_en (addr=*) 1 test run
pwm_regwen 75725976839654740565726549801988772397829650725123171969005510377463714178573 111
UVM_INFO @ 7247868363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---