Simulation Results: pwrmgr

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.13 %
  • code
  • 95.42 %
  • assert
  • 98.43 %
  • func
  • 97.53 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 94.48 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 42.028us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 31.618us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.310s 45.799us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.740s 21.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.850s 53.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 21.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.820s 633.088us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.820s 633.088us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.120s 30.485us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 58.017us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.690s 41.469us 1 1 100.00
pwrmgr_reset_invalid 0.750s 116.499us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.690s 41.469us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 129.325us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 62.083us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.500s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.080s 1495.952us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 21.283us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.080s 305.918us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.080s 305.918us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 31.618us 1 1 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 21.661us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 41.326us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 31.618us 1 1 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 21.661us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 41.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.920s 100.434us 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.920s 100.434us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.110s 762.310us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.680s 129.325us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.980s 708.351us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.780s 46.164us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.650s 107.011us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.130s 1798.970us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.660s 43.553us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.630s 55.338us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.640s 27.286us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.740s 70.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.950s 232.925us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 10.620s 13517.685us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 42095419431207475647231980525188382353565093880797765782140413898761345916449 91
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 78317464395333787220680904928134672956630688765163669842096744513374061670277 2450
UVM_INFO @ 13517684774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---