Simulation Results: rstmgr

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.56 %
  • code
  • 99.15 %
  • assert
  • 98.26 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.19 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.140s 120.625us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.860s 129.073us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.910s 478.822us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.550s 262.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.110s 142.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00
rstmgr_csr_aliasing 1.550s 262.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.680s 105.487us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.440s 465.376us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 139.749us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.110s 1441.336us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.110s 1441.336us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.110s 1441.336us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.110s 1441.336us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.620s 477.445us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.750s 63.231us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.900s 184.863us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.900s 184.863us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.860s 129.073us 1 1 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00
rstmgr_csr_aliasing 1.550s 262.740us 1 1 100.00
rstmgr_same_csr_outstanding 1.360s 284.819us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.860s 129.073us 1 1 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00
rstmgr_csr_aliasing 1.550s 262.740us 1 1 100.00
rstmgr_same_csr_outstanding 1.360s 284.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.820s 16827.667us 1 1 100.00
rstmgr_tl_intg_err 1.550s 536.449us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.820s 16827.667us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.820s 16827.667us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.550s 536.449us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.910s 110.695us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.190s 2649.378us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.970s 302.193us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.820s 16827.667us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 70.374us 1 1 100.00