Simulation Results: rv_timer

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.52 %
  • code
  • 100.00 %
  • assert
  • 98.09 %
  • func
  • 91.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.820s 472.453us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.600s 51.795us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 51.888us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.140s 36.945us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.800s 95.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.970s 94.801us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 51.888us 1 1 100.00
rv_timer_csr_aliasing 0.800s 95.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.880s 228.423us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.800s 226.407us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 6.920s 31368.168us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 6.920s 31368.168us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.900s 12904.032us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.520s 24.262us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 13.681us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.230s 31.024us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.230s 31.024us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 51.795us 1 1 100.00
rv_timer_csr_rw 0.560s 51.888us 1 1 100.00
rv_timer_csr_aliasing 0.800s 95.827us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 28.958us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 51.795us 1 1 100.00
rv_timer_csr_rw 0.560s 51.888us 1 1 100.00
rv_timer_csr_aliasing 0.800s 95.827us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 28.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 251.929us 1 1 100.00
rv_timer_tl_intg_err 1.120s 248.457us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.120s 248.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.530s 34.790us 1 1 100.00
max_value 1 1 100.00
rv_timer_max 0.580s 13.813us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 9.980s 1100.994us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 59459936161520144254803828816711486554411657567326655714355100156446386431028 76
UVM_INFO @ 228423054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---