Simulation Results: spi_device/2p

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.56 %
  • code
  • 94.02 %
  • assert
  • 95.37 %
  • func
  • 76.29 %
  • line
  • 98.88 %
  • branch
  • 98.18 %
  • cond
  • 95.92 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 57.280s 10133.117us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.180s 55.576us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.290s 204.817us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.960s 936.494us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.230s 106.893us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.830s 536.543us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.290s 204.817us 1 1 100.00
spi_device_csr_aliasing 4.230s 106.893us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 101.628us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.050s 65.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.660s 24.367us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.000s 23.131us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.670s 42.556us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.690s 48.233us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.690s 48.233us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.460s 586.612us 1 1 100.00
spi_device_tpm_sts_read 0.770s 64.464us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.940s 4011.554us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.480s 32.711us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.360s 1896.363us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.360s 1896.363us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.010s 985.661us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.010s 985.661us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.010s 985.661us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.010s 985.661us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.010s 985.661us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.580s 1787.224us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.290s 8601.936us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.290s 8601.936us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.290s 8601.936us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.080s 191.641us 1 1 100.00
spi_device_read_buffer_direct 5.500s 7790.792us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.290s 8601.936us 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 27.490s 2377.610us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.260s 666.969us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.260s 666.969us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 111.780s 24776.970us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 57.280s 10133.117us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 16.960s 9162.026us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 73.590s 62288.231us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 14.324us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.720s 13.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.570s 39.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.570s 39.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 55.576us 1 1 100.00
spi_device_csr_rw 2.290s 204.817us 1 1 100.00
spi_device_csr_aliasing 4.230s 106.893us 1 1 100.00
spi_device_same_csr_outstanding 1.210s 27.318us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 55.576us 1 1 100.00
spi_device_csr_rw 2.290s 204.817us 1 1 100.00
spi_device_csr_aliasing 4.230s 106.893us 1 1 100.00
spi_device_same_csr_outstanding 1.210s 27.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.990s 52.115us 1 1 100.00
spi_device_tl_intg_err 5.290s 475.864us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.290s 475.864us 1 1 100.00