Simulation Results: spi_host

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.14 %
  • code
  • 95.03 %
  • assert
  • 94.89 %
  • func
  • 89.50 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 4.000s 267.700us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.883us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 47.278us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 227.725us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 22.463us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 33.626us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 47.278us 1 1 100.00
spi_host_csr_aliasing 2.000s 22.463us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 23.294us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 15.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.613us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 1.000s 34.561us 1 1 100.00
spi_host_error_cmd 1.000s 21.179us 1 1 100.00
spi_host_event 30.000s 19194.817us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 934.451us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 934.451us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 934.451us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 94.000s 8627.086us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 163.627us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 28.539us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 934.451us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 934.451us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 4.000s 267.700us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 4.000s 267.700us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 15.000s 1237.989us 1 1 100.00
spien 1 1 100.00
spi_host_spien 16.000s 2314.220us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 17.000s 3273.520us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 68.034us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 1.000s 34.561us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 72.606us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 30.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 117.368us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 117.368us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.883us 1 1 100.00
spi_host_csr_rw 1.000s 47.278us 1 1 100.00
spi_host_csr_aliasing 2.000s 22.463us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 86.640us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.883us 1 1 100.00
spi_host_csr_rw 1.000s 47.278us 1 1 100.00
spi_host_csr_aliasing 2.000s 22.463us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 86.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 451.562us 1 1 100.00
spi_host_sec_cm 1.000s 155.794us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 451.562us 1 1 100.00