Simulation Results: sram_ctrl/main

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 95.94 %
  • assert
  • 97.82 %
  • func
  • 93.20 %
  • block
  • 95.00 %
  • line
  • 95.47 %
  • branch
  • 92.22 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 827.332us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 45.782us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 34.922us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 49.011us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 2546.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 34.922us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.646us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 116.000s 42409.665us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 71.000s 6435.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 23.000s 18825.697us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 89.000s 3357.532us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 150.000s 126023.048us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 6632.658us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 40.000s 12784.214us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 5599.116us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 703.209us 1 1 100.00
sram_ctrl_partial_access_b2b 327.000s 401663.657us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2673.297us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 820.671us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 6112.862us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1502.592us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 362.343us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 186.000s 24232.652us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 24.467us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 20.142us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 20.142us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.782us 1 1 100.00
sram_ctrl_csr_rw 1.000s 34.922us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.646us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.782us 1 1 100.00
sram_ctrl_csr_rw 1.000s 34.922us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.646us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3703.565us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 743.399us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 743.399us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1502.592us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1502.592us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 34.922us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5599.116us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5599.116us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5599.116us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 40.000s 12784.214us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 684.913us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3703.565us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 1320.974us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 827.332us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 827.332us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 5599.116us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 40.000s 12784.214us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 827.332us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1308.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 6.000s 10048.957us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [sram_ctrl_common_vseq] wait timeout occurred! 1 test run
sram_ctrl_stress_all_with_rand_reset 94801055955217553259581213359972026543419909581068204908280120542974871340778 92
UVM_INFO @ 10048957292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---