Simulation Results: sram_ctrl/ret

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.88 %
  • code
  • 83.30 %
  • assert
  • 97.53 %
  • func
  • 94.80 %
  • block
  • 93.66 %
  • line
  • 94.89 %
  • branch
  • 89.36 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 45.481us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 46.787us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.787us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 794.143us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.639us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 148.823us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 46.787us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.639us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 347.288us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 160.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 3002.437us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 82.000s 3421.845us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 444.973us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 3.000s 248.827us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 654.449us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 2.000s 77.386us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 149.052us 1 1 100.00
sram_ctrl_partial_access_b2b 170.000s 13674.822us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 69.260us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 179.183us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 148.851us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 269.215us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 43.995us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 19.000s 4303.789us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.883us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 42.980us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 42.980us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.787us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.787us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.639us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.787us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.787us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.639us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 837.761us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 287.179us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 287.179us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 269.215us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 269.215us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.787us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 2.000s 77.386us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 2.000s 77.386us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 2.000s 77.386us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 654.449us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 193.827us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 837.761us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 34.798us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.481us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.481us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 2.000s 77.386us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 654.449us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 45.481us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 504.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 1572.780us 1 1 100.00