Simulation Results: sysrst_ctrl

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.24 %
  • code
  • 94.32 %
  • assert
  • 96.46 %
  • func
  • 67.95 %
  • line
  • 98.12 %
  • branch
  • 97.92 %
  • cond
  • 95.43 %
  • toggle
  • 100.00 %
  • FSM
  • 80.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.230s 2109.512us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.690s 2491.863us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.700s 2431.168us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.870s 2368.554us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.340s 4008.912us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.970s 2035.787us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 69.070s 26876.412us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.040s 3189.289us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.300s 2065.783us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.970s 2035.787us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.040s 3189.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 186.550s 116485.036us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 28.790s 61426.038us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.290s 3325.083us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.680s 2877.267us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.270s 2509.037us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.680s 2201.247us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.460s 2846.064us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.680s 2611.812us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 29.830s 2055916.296us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 74.680s 38313.999us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 26.840s 14224.464us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.150s 2050.215us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.130s 2011.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.460s 2026.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.460s 2026.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.340s 4008.912us 1 1 100.00
sysrst_ctrl_csr_rw 4.970s 2035.787us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.040s 3189.289us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.340s 5108.673us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.340s 4008.912us 1 1 100.00
sysrst_ctrl_csr_rw 4.970s 2035.787us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.040s 3189.289us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.340s 5108.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 40.980s 22011.880us 1 1 100.00
sysrst_ctrl_tl_intg_err 41.840s 22252.410us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 41.840s 22252.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.250s 2860.269us 1 1 100.00