Simulation Results: uart

 
10/06/2026 15:30:31 DVSim: v1.49.9 sha: 26f59d7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.71 %
  • code
  • 95.87 %
  • assert
  • 97.98 %
  • func
  • 57.27 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.820s 534.670us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 38.810us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 15.083us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.370s 628.426us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.740s 454.924us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.880s 34.069us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 15.083us 1 1 100.00
uart_csr_aliasing 0.740s 454.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 16.850s 59653.726us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.820s 534.670us 1 1 100.00
uart_tx_rx 16.850s 59653.726us 1 1 100.00
parity_error 2 2 100.00
uart_intr 24.880s 17403.167us 1 1 100.00
uart_rx_parity_err 13.070s 43822.767us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 16.850s 59653.726us 1 1 100.00
uart_intr 24.880s 17403.167us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 102.500s 160496.414us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 132.040s 118093.459us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 51.410s 120765.720us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 24.880s 17403.167us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 24.880s 17403.167us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 24.880s 17403.167us 1 1 100.00
perf 1 1 100.00
uart_perf 81.340s 2201.796us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.450s 6523.261us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.450s 6523.261us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 7.040s 20723.798us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 53.580s 47171.388us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.580s 7600.386us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 24.930s 7174.306us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 227.950s 122421.652us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 85.570s 118293.824us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.620s 107.276us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.600s 29.231us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.160s 596.292us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.160s 596.292us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 38.810us 1 1 100.00
uart_csr_rw 0.580s 15.083us 1 1 100.00
uart_csr_aliasing 0.740s 454.924us 1 1 100.00
uart_same_csr_outstanding 0.710s 30.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 38.810us 1 1 100.00
uart_csr_rw 0.580s 15.083us 1 1 100.00
uart_csr_aliasing 0.740s 454.924us 1 1 100.00
uart_same_csr_outstanding 0.710s 30.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.760s 62.573us 1 1 100.00
uart_tl_intg_err 1.120s 108.392us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.120s 108.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 27.290s 13248.277us 1 1 100.00