Simulation Results

Simulation Results: adc_ctrl

11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
66.27 %

code
93.60 %

assert
92.38 %

func
12.82 %

line
98.74 %

branch
97.22 %

cond
87.47 %

toggle
98.10 %

FSM
86.49 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	2.500s	5912.604us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	0.970s	878.129us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.910s	370.361us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	40.210s	26357.631us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	624.343us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.010s	435.365us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.910s	370.361us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	624.343us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.840s	345.777us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.670s	308.436us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.800s	367.874us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	1.270s	457.204us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.810s	362.954us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.680s	370.941us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.240s	515.263us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.680s	355.456us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	4.060s	5061.688us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	15.500s	24123.208us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	8.490s	69114.538us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	3.940s	4998.574us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	1.180s	531.955us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.790s	344.319us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.640s	700.548us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.640s	700.548us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.970s	878.129us	1	1	100.00
	adc_ctrl_csr_rw	0.910s	370.361us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	624.343us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.890s	2432.260us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.970s	878.129us	1	1	100.00
	adc_ctrl_csr_rw	0.910s	370.361us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	624.343us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.890s	2432.260us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	3.350s	8659.850us	1	1	100.00
	adc_ctrl_tl_intg_err	4.570s	8704.454us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	4.570s	8704.454us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	4.400s	2707.361us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				8 test runs
	adc_ctrl_filters_polled	23349650773985442654433095674923985054461500384700732703729910935137930102107	386	UVM_INFO @ 345776658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	53954143865720105442365031363346872125977061218883422709141031035174276606812	386	UVM_INFO @ 308435620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	1658476224100909478670577365524213927586670005692050605874029734642584614082	386	UVM_INFO @ 367873756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	27876841522688918342179203525179349867974632036395403151326270866825083587565	386	UVM_INFO @ 457204465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	11785168470951010276271422916054972875713659593064476555493650996489604414191	386	UVM_INFO @ 362954328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	28043494284854163757074517908779065708791526293489446035477552050862186701011	386	UVM_INFO @ 370941280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	37726212076343807648730692925534317951484923230226065950044485452381036174345	386	UVM_INFO @ 355456301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	60985889944804357528643069231436676410847333409090267952430518815045893308626	386	UVM_INFO @ 515263068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---