Simulation Results: aes/masked

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.78 %
  • code
  • 94.66 %
  • assert
  • 98.38 %
  • func
  • 76.29 %
  • block
  • 95.08 %
  • line
  • 95.96 %
  • branch
  • 89.14 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 166.091us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 158.576us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 75.905us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 64.528us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 591.807us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 561.812us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 195.749us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 64.528us 1 1 100.00
aes_csr_aliasing 3.000s 561.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 158.576us 1 1 100.00
aes_config_error 3.000s 133.420us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 158.576us 1 1 100.00
aes_config_error 3.000s 133.420us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_b2b 13.000s 545.455us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 158.576us 1 1 100.00
aes_config_error 3.000s 133.420us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 56.974us 1 1 100.00
aes_config_error 3.000s 133.420us 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 234.418us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 649.039us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_sideload 3.000s 210.238us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 144.504us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 8.000s 363.733us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 214.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 122.497us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 122.497us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 75.905us 1 1 100.00
aes_csr_rw 1.000s 64.528us 1 1 100.00
aes_csr_aliasing 3.000s 561.812us 1 1 100.00
aes_same_csr_outstanding 2.000s 168.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 75.905us 1 1 100.00
aes_csr_rw 1.000s 64.528us 1 1 100.00
aes_csr_aliasing 3.000s 561.812us 1 1 100.00
aes_same_csr_outstanding 2.000s 168.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 170.668us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 268.555us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 536.332us 1 1 100.00
aes_tl_intg_err 2.000s 184.399us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 184.399us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 158.576us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
aes_core_fi 2.000s 97.073us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 133.420us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_core_fi 2.000s 97.073us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 66.998us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 82.006us 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 80.592us 1 1 100.00
aes_sideload 3.000s 210.238us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.006us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.006us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 82.006us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 82.006us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 82.006us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 80.592us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 153.234us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 153.234us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 153.234us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 153.234us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 124.835us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_ctr_fi 2.000s 52.529us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 153.234us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 153.234us 0 1 0.00
aes_control_fi 2.000s 67.464us 1 1 100.00
aes_cipher_fi 3.000s 109.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 8.535us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 39193464126940309829823073923484585005684063478467712077397194771963240899890 24036
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 44202885704162559564578833882826286613991492064142961366196229721897671584862 172
UVM_INFO @ 8534707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---