Simulation Results: aes/unmasked

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.51 %
  • code
  • 89.07 %
  • assert
  • 97.73 %
  • func
  • 75.72 %
  • block
  • 89.48 %
  • line
  • 91.98 %
  • branch
  • 79.65 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 140.609us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 62.611us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 157.511us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 63.825us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1490.092us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 305.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 140.110us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 63.825us 1 1 100.00
aes_csr_aliasing 1.000s 305.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 62.611us 1 1 100.00
aes_config_error 2.000s 115.485us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 62.611us 1 1 100.00
aes_config_error 2.000s 115.485us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_b2b 5.000s 134.787us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 62.611us 1 1 100.00
aes_config_error 2.000s 115.485us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 60.874us 1 1 100.00
aes_config_error 2.000s 115.485us 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 158.204us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 483.946us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_sideload 2.000s 148.237us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 95.456us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 199.222us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 59.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 74.965us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 74.965us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 157.511us 1 1 100.00
aes_csr_rw 2.000s 63.825us 1 1 100.00
aes_csr_aliasing 1.000s 305.517us 1 1 100.00
aes_same_csr_outstanding 2.000s 76.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 157.511us 1 1 100.00
aes_csr_rw 2.000s 63.825us 1 1 100.00
aes_csr_aliasing 1.000s 305.517us 1 1 100.00
aes_same_csr_outstanding 2.000s 76.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 125.673us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 110.027us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1153.395us 1 1 100.00
aes_tl_intg_err 2.000s 185.999us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 185.999us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 62.611us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
aes_core_fi 1.000s 66.520us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 115.485us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_core_fi 1.000s 66.520us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 206.468us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 60.397us 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 107.090us 1 1 100.00
aes_sideload 2.000s 148.237us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.397us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.397us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 60.397us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 60.397us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 60.397us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 107.090us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 468.466us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 468.466us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 468.466us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 468.466us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 89.215us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_ctr_fi 2.000s 70.973us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 468.466us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 468.466us 0 1 0.00
aes_control_fi 2.000s 71.638us 1 1 100.00
aes_cipher_fi 2.000s 49.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 471.557us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 42699730562114438525333224334807576734617055757496659236739392842790901323256 2605
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 86082235384406348276860014108946641168879230297644465752313017253941948625832 379
UVM_INFO @ 471556645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---