Simulation Results: alert_handler

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.28 %
  • code
  • 91.10 %
  • assert
  • 98.33 %
  • func
  • 78.40 %
  • line
  • 99.73 %
  • branch
  • 98.21 %
  • cond
  • 91.40 %
  • toggle
  • 87.12 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.180s 131.572us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.180s 37.955us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 160.010s 2548.784us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 175.240s 4450.519us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.370s 115.678us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.180s 37.955us 1 1 100.00
alert_handler_csr_aliasing 175.240s 4450.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 100.780s 2537.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 7.240s 1914.704us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 595.420s 13646.447us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 7.650s 332.888us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 46.420s 21774.287us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 22.460s 2055.882us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 91.410s 3546.839us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2291.470s 65196.886us 1 1 100.00
alert_handler_lpg_stub_clk 1931.450s 49928.300us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1080.160s 317074.340us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.740s 653.000us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.840s 312.073us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.070s 17.948us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 13.610s 1375.025us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 13.610s 1375.025us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.180s 131.572us 1 1 100.00
alert_handler_csr_rw 2.180s 37.955us 1 1 100.00
alert_handler_csr_aliasing 175.240s 4450.519us 1 1 100.00
alert_handler_same_csr_outstanding 25.570s 2446.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.180s 131.572us 1 1 100.00
alert_handler_csr_rw 2.180s 37.955us 1 1 100.00
alert_handler_csr_aliasing 175.240s 4450.519us 1 1 100.00
alert_handler_same_csr_outstanding 25.570s 2446.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 80.740s 2577.267us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 80.740s 2577.267us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 80.740s 2577.267us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 80.740s 2577.267us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 173.580s 8088.153us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
alert_handler_tl_intg_err 2.240s 46.915us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.240s 46.915us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 80.740s 2577.267us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 15.630s 374.879us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.650s 332.888us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2291.470s 65196.886us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.650s 332.888us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 595.420s 13646.447us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 595.420s 13646.447us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 14.900s 1381.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 103.050s 2673.143us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state 1 test run
alert_handler_ping_timeout 73170308431218919817737890869616428588906045751532711412775923321633894279682 103
UVM_INFO @ 3546838995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 62095781219120917242619559131680678229157036981034231275481350937379397476072 208
UVM_INFO @ 653000140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 19219263587391425171765057694596716464953035820943684038800545649629915829181 121
UVM_INFO @ 2673142736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---