Simulation Results

Simulation Results: chip

11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
73.13 %

code
84.70 %

assert
97.12 %

func
37.56 %

line
93.94 %

branch
92.26 %

cond
88.92 %

toggle
91.26 %

FSM
57.14 %

Validation stages

V1		88.89%
V2		76.98%
V2S		100.00%
V3		69.23%
unmapped		63.64%

16/18 passed

88.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	162.160s	3129.867us	1	1	100.00
	chip_sw_example_rom	82.380s	2204.431us	1	1	100.00
	chip_sw_example_manufacturer	172.600s	3478.262us	1	1	100.00
	chip_sw_example_concurrency	123.790s	2723.994us	1	1	100.00
csr_hw_reset				0	1	0.00
	chip_csr_hw_reset	181.040s	5558.726us	0	1	0.00
csr_rw				1	1	100.00
	chip_csr_rw	222.540s	4760.871us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	528.870s	8156.729us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4302.790s	33033.002us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	51.420s	2615.717us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4302.790s	33033.002us	1	1	100.00
	chip_csr_rw	222.540s	4760.871us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	7.390s	257.837us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	306.550s	4184.943us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	306.550s	4184.943us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	306.550s	4184.943us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	339.510s	4673.450us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	339.510s	4673.450us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	362.100s	4415.281us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	366.040s	3889.664us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	450.570s	5197.650us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	359.000s	5098.475us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	383.770s	4136.304us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1141.210s	14002.002us	1	1	100.00

214/278 passed

76.98 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	275.970s	5816.366us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	275.970s	5816.366us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	163.760s	3214.059us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	217.480s	6039.225us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	168.230s	4197.297us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	360.210s	7277.544us	1	1	100.00
	chip_tap_straps_testunlock0	328.130s	5451.307us	1	1	100.00
	chip_tap_straps_rma	200.630s	5166.116us	1	1	100.00
	chip_tap_straps_prod	713.670s	10611.868us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	151.160s	3019.566us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	752.070s	8685.462us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	429.530s	6358.920us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	429.530s	6358.920us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	533.700s	7567.536us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	657.880s	9189.685us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	309.390s	3919.807us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	606.200s	5711.946us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3939.210s	18838.905us	1	1	100.00
	chip_sw_aes_enc_jitter_en	190.610s	3431.687us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	636.860s	6325.234us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	185.770s	3294.997us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1769.430s	12771.798us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	199.670s	2848.405us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	428.890s	4957.192us	1	1	100.00
	chip_sw_clkmgr_jitter	195.280s	3260.359us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	185.130s	3294.464us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	356.580s	6122.136us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.460s	5480.548us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	176.540s	3515.658us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.460s	5480.548us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	141.930s	2813.537us	1	1	100.00
	chip_sw_aes_smoketest	142.960s	2465.272us	1	1	100.00
	chip_sw_aon_timer_smoketest	198.430s	3641.706us	1	1	100.00
	chip_sw_clkmgr_smoketest	200.230s	3295.328us	1	1	100.00
	chip_sw_csrng_smoketest	180.910s	3193.334us	1	1	100.00
	chip_sw_entropy_src_smoketest	936.840s	7046.178us	1	1	100.00
	chip_sw_gpio_smoketest	235.830s	3804.390us	1	1	100.00
	chip_sw_hmac_smoketest	275.640s	3764.428us	1	1	100.00
	chip_sw_kmac_smoketest	224.620s	3198.789us	1	1	100.00
	chip_sw_otbn_smoketest	1046.440s	8516.648us	1	1	100.00
	chip_sw_pwrmgr_smoketest	308.300s	6650.530us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	334.470s	6726.919us	1	1	100.00
	chip_sw_rv_plic_smoketest	136.390s	2521.014us	1	1	100.00
	chip_sw_rv_timer_smoketest	177.090s	3518.096us	1	1	100.00
	chip_sw_rstmgr_smoketest	162.870s	2908.224us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	122.140s	2935.202us	1	1	100.00
	chip_sw_uart_smoketest	138.660s	2805.274us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	132.220s	3148.283us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	420.890s	4887.001us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8380.020s	63039.254us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3269.820s	16222.085us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	40.577s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	184.810s	3184.648us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	210.550s	3928.102us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7102.610s	56112.980us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7955.430s	57124.716us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	246.870s	4089.584us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	246.870s	4089.584us	1	1	100.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	4302.790s	33033.002us	1	1	100.00
	chip_same_csr_outstanding	1323.420s	14991.401us	1	1	100.00
	chip_csr_hw_reset	181.040s	5558.726us	0	1	0.00
	chip_csr_rw	222.540s	4760.871us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	4302.790s	33033.002us	1	1	100.00
	chip_same_csr_outstanding	1323.420s	14991.401us	1	1	100.00
	chip_csr_hw_reset	181.040s	5558.726us	0	1	0.00
	chip_csr_rw	222.540s	4760.871us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	44.960s	2065.400us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.470s	44.961us	1	1	100.00
	xbar_smoke_large_delays	45.050s	7027.159us	1	1	100.00
	xbar_smoke_slow_rsp	37.890s	4254.419us	1	1	100.00
	xbar_random_zero_delays	8.590s	118.577us	1	1	100.00
	xbar_random_large_delays	143.370s	21714.332us	1	1	100.00
	xbar_random_slow_rsp	71.410s	7896.826us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	14.720s	210.556us	1	1	100.00
	xbar_error_and_unmapped_addr	21.200s	337.070us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	37.080s	1695.866us	1	1	100.00
	xbar_error_and_unmapped_addr	21.200s	337.070us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	70.630s	2794.369us	1	1	100.00
	xbar_access_same_device_slow_rsp	279.520s	35760.294us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	12.050s	189.914us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	181.670s	7990.397us	1	1	100.00
	xbar_stress_all_with_error	30.340s	623.260us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	365.870s	6783.463us	1	1	100.00
	xbar_stress_all_with_reset_error	171.440s	668.645us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3269.820s	16222.085us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2472.690s	23871.510us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3060.650s	15429.142us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	156.813s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	9.133s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	8.330s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	34.782s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	8.685s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	48.590s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.233s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.619s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	8.819s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.320s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	171.852s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	81.522s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	23.657s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	48.575s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.593s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.810s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.810s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	19.350s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.580s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	20.430s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.500s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.890s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.720s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.230s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.150s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.850s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.520s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	22.890s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.770s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.560s	10.300us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	182.621s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	74.094s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	65.515s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	95.345s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	63.317s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	6044.370s	29426.642us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6058.460s	30835.964us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6098.440s	29288.821us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3228.500s	16158.468us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3054.370s	35384.221us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3054.370s	35384.221us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	165.600s	3128.525us	1	1	100.00
	chip_sw_aes_enc_jitter_en	190.610s	3431.687us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	171.530s	2972.324us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	162.390s	3275.397us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	932.620s	8489.508us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	180.350s	3160.172us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	345.320s	4835.639us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	602.750s	4945.139us	1	1	100.00
	chip_plic_all_irqs_10	301.540s	4283.711us	1	1	100.00
	chip_plic_all_irqs_20	383.590s	4692.565us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	179.270s	3577.799us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1334.140s	15405.230us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	338.380s	4485.158us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	170.980s	3523.754us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.136s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1213.610s	8813.037us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	868.750s	7060.879us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	802.020s	7986.513us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7864.210s	256574.701us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	278.690s	3812.062us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	308.300s	6650.530us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	278.690s	3812.062us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	591.620s	7969.558us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	591.620s	7969.558us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	326.500s	6914.320us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	291.510s	4759.218us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	615.060s	6075.814us	1	1	100.00
	chip_sw_aes_idle	162.390s	3275.397us	1	1	100.00
	chip_sw_hmac_enc_idle	217.090s	3668.419us	1	1	100.00
	chip_sw_kmac_idle	171.710s	2945.537us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	301.820s	4186.803us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	309.830s	5016.269us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	311.290s	4139.629us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	294.620s	4656.709us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	669.920s	11019.227us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	393.020s	3888.963us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	393.560s	4659.264us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	385.020s	4491.902us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.900s	4908.742us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	387.650s	4385.731us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	429.860s	5103.491us	1	1	100.00
	chip_sw_ast_clk_outputs	533.700s	7567.536us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	306.250s	7240.903us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	385.020s	4491.902us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.900s	4908.742us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	309.390s	3919.807us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	606.200s	5711.946us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3939.210s	18838.905us	1	1	100.00
	chip_sw_aes_enc_jitter_en	190.610s	3431.687us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	636.860s	6325.234us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	185.770s	3294.997us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1769.430s	12771.798us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	199.670s	2848.405us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	428.890s	4957.192us	1	1	100.00
	chip_sw_clkmgr_jitter	195.280s	3260.359us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	162.680s	3002.767us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	401.040s	5195.510us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	636.650s	7123.163us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4047.430s	25121.706us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	163.480s	2623.928us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	181.680s	3142.501us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	629.030s	8337.123us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	208.730s	4004.757us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	392.950s	5002.903us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1266.430s	20374.614us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	6625.540s	62969.201us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	533.700s	7567.536us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	423.440s	5451.047us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	266.880s	3647.146us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1213.610s	8813.037us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2191.420s	24408.867us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	179.480s	3158.957us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	435.980s	6266.932us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	195.090s	3544.902us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	4066.600s	22618.800us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	175.590s	3585.308us	1	1	100.00
	chip_sw_edn_entropy_reqs	684.060s	6353.208us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	175.590s	3585.308us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2191.420s	24408.867us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	178.190s	3246.814us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1282.070s	20750.755us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	583.900s	5865.594us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	606.200s	5711.946us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	364.800s	4024.732us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	309.390s	3919.807us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3314.060s	43614.246us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1282.070s	20750.755us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	205.950s	3338.361us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3314.060s	43614.246us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	329.400s	13212.091us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	529.480s	5197.547us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	440.680s	4719.616us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	440.680s	4719.616us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	182.230s	2885.024us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	185.770s	3294.997us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	217.090s	3668.419us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1717.780s	12018.492us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1738.180s	12018.315us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	374.460s	4906.052us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	315.460s	4871.475us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	344.230s	5245.651us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	317.850s	4341.690us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1769.430s	12771.798us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1512.870s	11536.979us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	932.620s	8489.508us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4816.640s	20018.542us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	140.110s	3304.611us	1	1	100.00
	chip_sw_kmac_mode_kmac	213.410s	3110.926us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	199.670s	2848.405us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	151.760s	2456.112us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1557.200s	10994.182us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	171.710s	2945.537us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	345.320s	4835.639us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	360.210s	7277.544us	1	1	100.00
	chip_tap_straps_rma	200.630s	5166.116us	1	1	100.00
	chip_tap_straps_prod	713.670s	10611.868us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	173.410s	3651.220us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1582.510s	12437.750us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	145.120s	3319.216us	0	1	0.00
	chip_sw_flash_rma_unlocked	3314.060s	43614.246us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	250.030s	3467.515us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	540.430s	6306.188us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	499.790s	7671.623us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	483.360s	7210.899us	0	1	0.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.030s	9709.954us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	566.620s	7863.018us	1	1	100.00
	chip_prim_tl_access	329.400s	13212.091us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	306.250s	7240.903us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	393.020s	3888.963us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	393.560s	4659.264us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	385.020s	4491.902us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.900s	4908.742us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	387.650s	4385.731us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	429.860s	5103.491us	1	1	100.00
	chip_tap_straps_dev	360.210s	7277.544us	1	1	100.00
	chip_tap_straps_rma	200.630s	5166.116us	1	1	100.00
	chip_tap_straps_prod	713.670s	10611.868us	1	1	100.00
	chip_rv_dm_lc_disabled	59.990s	2392.661us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	140.830s	3324.219us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	93.980s	3191.450us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	76.390s	3187.606us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	119.410s	3752.972us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1765.220s	31886.012us	1	1	100.00
	chip_rv_dm_lc_disabled	59.990s	2392.661us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	681.020s	10864.934us	0	1	0.00
	chip_sw_lc_walkthrough_prod	684.400s	9324.115us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	742.460s	9824.850us	1	1	100.00
	chip_sw_lc_walkthrough_rma	393.850s	6897.262us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1765.220s	31886.012us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	83.060s	2906.359us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	60.480s	1926.123us	1	1	100.00
	rom_volatile_raw_unlock	97.036s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3919.200s	17094.895us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3939.210s	18838.905us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	615.060s	6075.814us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	615.060s	6075.814us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	615.060s	6075.814us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	272.590s	4024.371us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1282.070s	20750.755us	1	1	100.00
	chip_sw_otbn_mem_scramble	272.590s	4024.371us	1	1	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	321.360s	4537.564us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	130.250s	3213.581us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1282.070s	20750.755us	1	1	100.00
	chip_sw_otbn_mem_scramble	272.590s	4024.371us	1	1	100.00
	chip_sw_keymgr_key_derivation	1772.570s	13044.183us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	321.360s	4537.564us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	130.250s	3213.581us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	304.800s	4164.942us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	173.410s	3651.220us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	250.030s	3467.515us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	540.430s	6306.188us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	499.790s	7671.623us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	483.360s	7210.899us	0	1	0.00
	chip_sw_lc_ctrl_transition	732.060s	11910.151us	1	1	100.00
	chip_prim_tl_access	329.400s	13212.091us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	329.400s	13212.091us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	922.760s	8476.613us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	59.590s	2242.189us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1135.980s	25445.075us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	251.420s	7344.276us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	314.440s	7587.302us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	344.400s	7337.224us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1066.050s	23922.328us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	179.560s	5500.312us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	591.620s	7969.558us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	910.520s	11049.921us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	325.190s	5526.531us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	59.590s	2242.189us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	346.010s	5839.826us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	238.830s	6158.870us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	270.620s	6249.757us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	124.670s	2837.080us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	2002.170s	23758.164us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	660.490s	8806.088us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	965.260s	12040.692us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1904.790s	24201.026us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	157.580s	3253.027us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.030s	9709.954us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.030s	9709.954us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	965.260s	12040.692us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	2002.170s	23758.164us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	325.190s	5526.531us	1	1	100.00
	chip_sw_pwrmgr_smoketest	308.300s	6650.530us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	342.360s	5314.703us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	440.590s	5865.994us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	257.450s	5121.582us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1334.140s	15405.230us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	186.270s	3696.324us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	868.750s	7060.879us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	453.050s	4604.350us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	526.660s	5373.885us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	225.460s	3121.834us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	130.250s	3213.581us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	440.590s	5865.994us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	440.590s	5865.994us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1659.500s	17447.685us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	910.860s	13555.345us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	342.360s	5314.703us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	247.320s	3529.776us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	253.240s	5720.881us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	200.630s	5166.116us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	59.990s	2392.661us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	602.750s	4945.139us	1	1	100.00
	chip_plic_all_irqs_10	301.540s	4283.711us	1	1	100.00
	chip_plic_all_irqs_20	383.590s	4692.565us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	170.970s	3190.860us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	196.530s	3629.358us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3269.820s	16222.085us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	450.920s	6889.832us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	175.730s	3259.242us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	235.790s	3661.359us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	203.020s	3049.897us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	321.360s	4537.564us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	428.890s	4957.192us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	490.310s	9805.704us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	573.140s	8303.390us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	566.620s	7863.018us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
	chip_sw_data_integrity_escalation	429.530s	6358.920us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	660.490s	8806.088us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.760s	25598.764us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	172.510s	3410.823us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	254.670s	3258.542us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	374.440s	5084.406us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.760s	25598.764us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1111.760s	25598.764us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2384.780s	20969.511us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2384.780s	20969.511us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	285.190s	6585.980us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3054.370s	35384.221us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	129.490s	2133.802us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	122.550s	2149.083us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	297.930s	4619.580us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	349.070s	4241.155us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1074.430s	8114.114us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5674.100s	31487.432us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1848.400s	12485.267us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	189.020s	2646.045us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	181.340s	3389.406us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	98.100s	2503.484us	1	1	100.00

18/26 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9861.730s	71722.692us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1150.210s	6596.559us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	215.950s	5306.770us	0	1	0.00
	rom_e2e_jtag_debug_dev	241.300s	4491.443us	0	1	0.00
	rom_e2e_jtag_debug_rma	211.030s	4747.143us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	55.040s	1843.008us	0	1	0.00
	rom_e2e_jtag_inject_dev	219.820s	5819.297us	1	1	100.00
	rom_e2e_jtag_inject_rma	84.070s	2120.892us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	48.971s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	241.350s	3521.911us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	322.230s	3467.906us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	667.390s	4843.584us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1240.910s	9640.330us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	248.630s	2537.050us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	644.770s	5121.739us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	55.230s	1966.786us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	178.990s	2484.855us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	336.940s	5954.041us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	363.670s	4442.855us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	965.260s	12040.692us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	215.950s	5306.770us	0	1	0.00
	rom_e2e_jtag_debug_dev	241.300s	4491.443us	0	1	0.00
	rom_e2e_jtag_debug_rma	211.030s	4747.143us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	386.610s	5481.779us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	439.190s	6476.060us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6015.320s	39023.141us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6015.320s	39023.141us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	138.600s	3708.147us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	339.510s	4673.450us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2802.180s	18742.054us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	216.580s	3178.354us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.080s	10.300us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.320s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	129.700s	2723.776us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	232.320s	3776.456us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	191.160s	3406.317us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.550s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	211.700s	3035.329us	1	1	100.00
	ate_bootstrap_flash_erase	552.990s	10010.140us	0	1	0.00
	ate_bootstrap_one_frame	6689.210s	44739.074us	1	1	100.00
	ate_bootstrap_disjoint	10134.240s	84714.157us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	111104362589518485229800599846937094878917805468510033570142755489837058671909	None	---- STDERR ---- Another command (pid=2085677) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	51564112110313411008868037189597187285217043993461406791286892310760260601741	None	Another command (pid=646783) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=629523) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=566551) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	97177439172420335362876216904421784835279180052898848192336204646933675352480	None	Another command (pid=610107) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=567785) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=611340) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	17472637695289667078224403443722115192036083187822724635068699978069056771792	None	---- STDERR ---- Another command (pid=620597) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	62880543942171636823374329548425440448949506289279377720410430507272779613002	None	Another command (pid=684714) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=669538) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=673219) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	31769372436756981459280563861827657859418073122372120053954040166258073675022	None	Another command (pid=621625) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=624755) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=624395) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	59158596538976146168962778741372529742550061299920042435581368802931184752600	None	---- STDERR ---- Another command (pid=382921) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	37522805532791552681214114451015679830449638500182579742085880911636090610888	None	Another command (pid=592291) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=579251) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=593654) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	26043200367053655622592578581454278981193725534545126724556338089075800077093	None	Another command (pid=584158) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=564024) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=585177) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	75535177429679792679810936075229491502411069009242541898001427194132270461951	None	---- STDERR ---- Another command (pid=588578) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=579251) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	34725484637197348691326891544670181711824265766153826416278121370859447153004	None	---- STDERR ---- Another command (pid=610107) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	110101291643906414173097505307948139294070675260162729538627502512706443209990	None	Another command (pid=647636) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=629523) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=566551) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	98421372217880096366485511962926662106791980871911858951099681396571202590705	None	Another command (pid=705752) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=728327) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=724436) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	35957759041491017653245435126971098970229124153053047231788381545759680750750	None	Another command (pid=604323) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=609246) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=565422) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	53083398102460287127170053853411567948926130875468535021524206356250352075829	None	---- STDERR ---- Another command (pid=646655) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=664551) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	494146758129020105055454994479206088595949888866021308559511331062679258150	None	Another command (pid=582372) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=581071) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=584158) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	75586274515992198754811656646568818482042528730090946511874810994790352359593	None	Another command (pid=667349) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=614030) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=673416) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	63479746175743315674125714322907121747072174879177017406833841009077022189513	None	Another command (pid=442269) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=471477) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=470748) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	45524590229131016726986074191503567003797095557112827969348379556568626601766	None	Another command (pid=471477) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=470748) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=473154) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	104462336815240719092548417900945840749115590268333001151935294708785014104135	None	Another command (pid=621625) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=624755) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=624395) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	69481189435433341873259245666688855970786163504114765568254541084176442230176	None	---- STDERR ---- Another command (pid=471477) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=470748) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	22641812951231381013037650920173384243961765577075554109168216887186660006855	None	Another command (pid=470748) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=490121) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=465274) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	24911663354806681293034749023342928533243714814051296333624688482777570862736	None	Another command (pid=382921) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=451416) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=412517) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	59921182578924124050524554711534771377337036086774061230826807696353916416114	None	Another command (pid=400355) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=412517) is running. Waiting for it to complete on the server (server_pid=300970)... Another command (pid=456534) is running. Waiting for it to complete on the server (server_pid=300970)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	81557514549979959270180021877223120980444115916503234870983301460042648987070	363	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	100543874954402624947792222670106247838743488250353132907486762334542046790080	368	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	70651883977169505025069511967367546071662693884448933591927258824285656969292	363	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	99665695890408695946035170566256624826424006866870526178542137186949428400345	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	53249438290641898005760934552749370068871944819496414386646870569979348835082	327	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	40295283894446376064405444622951408806144098057962468872099747125370514347978	327	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9358058676546675807114671260650850123516344019384733378327161285049315303891	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	24735170576763597956764610760276450370650590920930528353272467716564302661886	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	77271710862048939933044282887075580034040580644010926653679686341240579353562	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	68021572990137824446640165467512683997442965679989084113246408436027230374499	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	68334648667391422661893802037931475034600180824982405957131866646767480502599	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	94828392782006252985078555650212316374982186362097607063062743714992732034101	369	UVM_INFO @ 10864.933601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	87025232989526122225710585544575436523367258950131575153955645996047824235611	369	UVM_INFO @ 9324.114708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	48937615434359371728731281031109430471292872697991423926392426178876624465493	341	UVM_INFO @ 6897.261700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	37313283051967141759928581516667731196123693901151554317110918911205129325306	314	UVM_ERROR @ 5500.312500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5500.312500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	82962813228278202848151878075889240571635675066693090715127555695397668791331	325	UVM_ERROR @ 7587.302000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7587.302000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13849162373516729299422329812679612335624396031093861863860753072618491912414	316	UVM_ERROR @ 6158.870000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6158.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	12178049398983368847513579861005796720275081559451349644014186838963628959199	310	UVM_INFO @ 12018.492067 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	88041169815801509099686935096275666510658432049425961286408873954114734718696	310	UVM_INFO @ 12018.314798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	99990326170996507403182325944004680522553786313917249588615511290194193456380	336	UVM_INFO @ 20018.541554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	52258291323901880451179023475433155498163464075854847500785404049087623048455	325	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	85271787197830249249927404960376808983838990171654346998505880085392843121430	327	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	94583008175570602156228977220206020278558156753058151128840938640149134576386	327	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	44464341057081212424273786031129708148151743209880004020219505527403259161590	316	UVM_ERROR @ 2484.855354 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2484.855354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	7718661734514006636534987555089520235996662892857508674836832699147349427620	312	UVM_ERROR @ 3158.957352 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3158.957352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	32666048320838976040605173028444965188713666311792279981426558667661534556566	365	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	94720717620226595836255945637815612079267584804382589238991563230239785473717	327	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	75500248021859678140225022427351558797452826567998032074361153213865439537961	367	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	24729822890562383262981079329892326167339248250242922568477368833872956387236	325	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	69149474192295141613113785146506287540588470757308157497769953379687652493824	301	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	89623157438715878562439217693216113216747624650830004633857128864844138433328	451	UVM_INFO @ 3214.058500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	6318933180387368487540883491882740534804832731056539109968152329685044654269	327	UVM_INFO @ 3259.242464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	84748765939206430241478194674454190482647516972196640128498846127678027691202	309	UVM_INFO @ 3319.216264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	85038868617227404898963406668761484477776673440778555601141570376924666141423	342	UVM_INFO @ 7210.898608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	53914216944151379808977125302183516170866978345782903197404453861212478811191	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	953292494448670800092232222006137633146571082947613621089338290635053218673	303	UVM_ERROR @ 2242.189308 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2242.189308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	70440189334915185971566249899461524468033709166479189215506481268878909829492	313	UVM_ERROR @ 2837.080000 us: (rom_ctrl.sv:578) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2837.080000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	111533054707686221218174052429566833658394818049509299754525443936038320453702	332	UVM_INFO @ 35384.221348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	57640967314233964029068950325536561798772651529785340324033618848835648544949	307	UVM_INFO @ 3160.171864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	4665279408921467526566765212603894363752545876460893084473472529100087225453	308	UVM_INFO @ 3523.753524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	42371024712862615465004065313622089187691304580497660986479088886007590111353	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	111315647799426821240483788870252183614714269179107068335541711576573913536400	343	UVM_INFO @ 3521.910611 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	44814182079308382631140781338890620894045662183368499056283349380021557547711	215	UVM_INFO @ 2392.660875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	110977060155625625123184182621134188346308992922997655900138779778124048585593	312	UVM_INFO @ 3184.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	43052652265431361363143851455323097750657937944860903900222923306224712344747	318	UVM_INFO @ 3928.102000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	89445617542389883237058474107016848446897277787103811435506857126504677030185	327	UVM_INFO @ 9189.684982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	35114415297439622145563876806684516812693955826933564291375793021892290238561	272	UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	3546521091320975502878737005326627125270712257160654301463755257245876272895	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	112237863316018470513858589160327257476229211637090161974507369752025032618519	326	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds				1 test run
	rom_e2e_jtag_debug_test_unlocked0	113138753097231632563749087837282411949248031774201907279012721670604141607698	318	UVM_INFO @ 5306.769640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	745271673507216367192196875196475688359502937539373833516978379202911038003	327	UVM_ERROR @ 4887.000704 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4887.000704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				1 test run
	chip_csr_hw_reset	55003750377657815206180409654020978002245238858012674890299693742063062119321	239	UVM_ERROR @ 5558.725533 us: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 5558.725533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_csr_mem_rw_with_rand_reset	28873172184947292638385014062550973821252861417988418855514970030508656746907	224	TL item was: req: (cip_tl_seq_item@31678) { a_addr: 'h1063c a_data: 'hac2dcd07 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1bac3 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2615.716968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---