Simulation Results: clkmgr

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.77 %
  • code
  • 97.31 %
  • assert
  • 93.79 %
  • func
  • 84.22 %
  • line
  • 98.16 %
  • branch
  • 97.85 %
  • cond
  • 91.37 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.900s 87.426us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 76.111us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 9.410s 2994.483us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.980s 23.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 48.980us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
clkmgr_csr_aliasing 0.980s 23.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.710s 17.794us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.700s 14.559us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.810s 32.104us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.750s 19.295us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.900s 87.426us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.020s 1600.827us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.160s 184.655us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.020s 1600.827us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.180s 328.469us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.760s 16.837us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.180s 27.398us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.180s 27.398us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 76.111us 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
clkmgr_csr_aliasing 0.980s 23.803us 1 1 100.00
clkmgr_same_csr_outstanding 1.300s 173.994us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 76.111us 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
clkmgr_csr_aliasing 0.980s 23.803us 1 1 100.00
clkmgr_same_csr_outstanding 1.300s 173.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 26.060s 10013.834us 0 1 0.00
clkmgr_tl_intg_err 2.270s 234.773us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 764.940s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 764.940s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 764.940s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 764.940s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.770s 273.191us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.270s 234.773us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.020s 1600.827us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.160s 184.655us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 764.940s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.050s 150.097us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.810s 37.186us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.800s 44.724us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.020s 105.770us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.990s 67.319us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 26.060s 10013.834us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 30.150us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 26.060s 10013.834us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.750s 336.485us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 28.160s 7177.607us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 106661387974710916306876465239899737218042604354266798469897997607756185469856 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 7848982682226900698212635578621216551781434008668344133721408419967587715836 83
UVM_INFO @ 10013834024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---