Simulation Results: edn/edn0

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.79 %
  • code
  • 83.88 %
  • assert
  • 96.96 %
  • func
  • 82.54 %
  • line
  • 97.77 %
  • branch
  • 92.47 %
  • cond
  • 87.58 %
  • toggle
  • 86.18 %
  • FSM
  • 55.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 17.490us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.070s 30.475us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 17.610us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.940s 48.793us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.130s 23.306us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.850s 25.805us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 17.610us 1 1 100.00
edn_csr_aliasing 1.130s 23.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.730s 129.187us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.730s 129.187us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.730s 129.187us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.020s 23.027us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 99.860us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 19.721us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 21.323us 1 1 100.00
edn_disable_auto_req_mode 0.900s 70.716us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.170s 597.199us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.950s 29.984us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 34.816us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.020s 70.061us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.020s 70.061us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.070s 30.475us 1 1 100.00
edn_csr_rw 0.880s 17.610us 1 1 100.00
edn_csr_aliasing 1.130s 23.306us 1 1 100.00
edn_same_csr_outstanding 1.170s 131.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.070s 30.475us 1 1 100.00
edn_csr_rw 0.880s 17.610us 1 1 100.00
edn_csr_aliasing 1.130s 23.306us 1 1 100.00
edn_same_csr_outstanding 1.170s 131.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
edn_tl_intg_err 1.980s 174.210us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 28.635us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 99.860us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 99.860us 1 1 100.00
edn_sec_cm 7.170s 607.626us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 99.860us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.980s 174.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 76.420s 4051.126us 1 1 100.00