Simulation Results: edn/edn1

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.11 %
  • code
  • 83.00 %
  • assert
  • 98.70 %
  • func
  • 79.62 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.31 %
  • toggle
  • 87.61 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 17.879us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 18.013us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.940s 22.643us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.550s 3095.798us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 17.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 32.685us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.940s 22.643us 1 1 100.00
edn_csr_aliasing 1.080s 17.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.820s 81.297us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.820s 81.297us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.820s 81.297us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 29.595us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.230s 34.590us 1 1 100.00
errs 1 1 100.00
edn_err 1.080s 39.923us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 44.340us 1 1 100.00
edn_disable_auto_req_mode 1.250s 103.686us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.130s 161.293us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 19.188us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 25.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.920s 69.600us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.920s 69.600us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 18.013us 1 1 100.00
edn_csr_rw 0.940s 22.643us 1 1 100.00
edn_csr_aliasing 1.080s 17.258us 1 1 100.00
edn_same_csr_outstanding 1.040s 154.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 18.013us 1 1 100.00
edn_csr_rw 0.940s 22.643us 1 1 100.00
edn_csr_aliasing 1.080s 17.258us 1 1 100.00
edn_same_csr_outstanding 1.040s 154.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
edn_tl_intg_err 1.850s 115.218us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 174.496us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.230s 34.590us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.230s 34.590us 1 1 100.00
edn_sec_cm 2.090s 1027.686us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.230s 34.590us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.850s 115.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 37.490s 2135.931us 1 1 100.00